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VIPER20B Fiches technique(PDF) 13 Page - STMicroelectronics |
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VIPER20B Fiches technique(HTML) 13 Page - STMicroelectronics |
13 / 17 page network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by putting the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption doesn’t exceed 0.5mA. Figure 14 shows a typical application of this function, with a latched shut down. Once the ”Shutdown” signal has been activated, the device remains in the off state until the input voltage is removed. TRANSCONDUCTANCE ERROR AMPLIFIER The VIPer30B includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (VDD). Thus: Gm = ∂ ICOMP ∂ VDD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: ZCOMP = ∂ VCOMP ∂ ICOMP = 1 Gm x ∂ VCOMP ∂ VDD This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: AVOL =Gm xZCOMP where Gm value for VIPer20B is 1.5 mA/V typically. Gm is well defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define more accurately the transfer function F of the error amplifier, according to the following equation, very similar to the one above: F(S) = Gm x Z(S) The error amplifier frequency response is reported in figure 8 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330 K Ω. More complex impedance can be connected on the COMP pin to achieve different compensation laws. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated on figure 15. As shown in figure 15 an additional noise filtering capacitor of 2.2 nF is generally needed to avoid any high frequency interference. It can be also interesting to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. Figure 16 shows such a configuration. Note that R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. EXTERNAL CLOCK SYNCHRONIZATION: The OSC pin provides a synchronisation capability, when connected to an external frequency source. Figure 17 shows one possible Figure 14: Latched Shut Down - + 13V OSC COMP SOURCE DRAIN VDD VIPer Shutdown Q1 Q2 R1 R2 R3 R4 D1 FC00442 Figure 13: Mixed Soft Start and Compensation - + 13V OSC COMP SO URCE DRAIN VDD VIPer R1 C1 + C2 D1 R2 R3 D2 D3 + C3 AUXILIARY WINDING FC00432 C4 VIPer20B / VIPer20BSP 13/17 |
Numéro de pièce similaire - VIPER20B |
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Description similaire - VIPER20B |
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