SA306

0

SA306U

P r o d u c t I n n o v a t i o n F r o m

2.LAYOUTCONSIDERATIONS

Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing

ensures normal operation. Poor routing and bypassing can cause erratic and low efficiency operation as well as

ringing at the outputs.

The V

pins. Total inductance of the routing from the capacitor to the V

vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output

current should be placed near the SA306 as well. Capacitor types rated for switching applications are the only types

that should be considered. Note that phases B & C share a V

reflect the sum of B & C phase current.

The bypassing requirements of the V

mount ceramic capacitor (X7R or NPO) connected directly to the V

SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way

that there is no motor current flowing in the logic and signal ground traces as parasitic resistances in the small

signal routing can develop sufficient voltage drops to erroneously trigger input transitions. Alternatively, a ground

plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This

isolates noise between signal and power ground traces and prevents high currents from passing between the plane

sections.

Unused area on the top and bottom PCB planes should be filled with solid or hatched copper to minimize inductive

coupling between signals. The copper fill may be left unconnected, although a ground plane is recommended.

2.2FAULTINDICATIONS

In the case of either an over-temperature or short circuit fault, the SA306 will take no action to disable the outputs.

Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made re-

garding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the

processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate

response, and would typically be connected to a GPIO, or keyboard Interrupt pin of the processor. In this case,

the processor would recognize the condition as an external interrupt, which could be processed in software via an

Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the

disable inputs on the SA306.

Figure 6 shows an external SR flip-flop which pro-

vides a hard wired shutdown of all outputs in re-

sponse to a fault indication. An SC or TEMP fault sets

the latch, pulling the disable pin high. The processor

clears the latched condition with a GPIO. This circuit

can be used in safety critical applications to remove

software from the fault-shutdown loop, or simply to

reduce processor overhead.

In applications which may not have available GPIO,

the TEMP pin may be externally connected to the

adjacent DIS1 pin. If the device temperature reaches

~135ºC all outputs will be disabled, de-energizing the

motor. The SA306 will re-energize the motor when

the device temperature falls below approximately 95ºC. The TEMP pin hysteresis is wide to reduce the likelihood

of thermal oscillations which can greatly reduce the life of the device.

2.3 UNDER-VOLTAGE LOCKOUT

The undervoltage lockout condition results in the SA306 unilaterally disabling all output FETs until V

the UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lock-

FIgURE6.ExTERNALFAULTLATCh

CIRCUIT

SA306

PROCESSOR

INTERRUPT

GPIO

PWM

SC

DIS2

TEMP

LATCHED FAULT

FAULT RESET