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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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CS4265 Fiches technique(PDF) 36 Page - Cirrus Logic |
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CS4265 Fiches technique(HTML) 36 Page - Cirrus Logic |
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36 / 56 page  36 DS657F2 CS4265 6.2.4 Power-Down DAC (Bit 1) Function: The DAC pair will remain in a reset state whenever this bit is set. 6.2.5 Power-Down Device (Bit 0) Function: The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation can occur. The contents of the control registers are retained when the device is in power-down. 6.3 DAC Control - Address 03h 6.3.1 DAC Digital Interface Format (Bits 5:4) Function: The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital In- terface Format and the options are detailed in Table 6 and Figures 5-7. 6.3.2 Mute DAC (Bit 2) Function: The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is active high, it should be noted that the MUTEC pin is active low. The common mode voltage on the outputs will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the DACSoft and DACZero bits in the DAC Control 2 register. 76 543 21 0 Reserved Reserved DAC_DIF1 DAC_DIF0 Reserved MuteDAC DeEmph Reserved DAC_DIF1 DAC_DIF0 Description Format Figure 0 0 Left Justified, up to 24-bit data (default) 0 5 0 1 I²S, up to 24-bit data 1 6 1 0 Right-Justified, 16-bit Data 2 7 1 1 Right-Justified, 24-bit Data 3 7 Table 6. DAC Digital Interface Formats |
Numéro de pièce similaire - CS4265_07 |
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Description similaire - CS4265_07 |
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