Moteur de recherche de fiches techniques de composants électroniques |
|
AD9520-5BCPZ Fiches technique(PDF) 2 Page - Analog Devices |
|
AD9520-5BCPZ Fiches technique(HTML) 2 Page - Analog Devices |
2 / 80 page AD9520-5 Rev. 0 | Page 2 of 80 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 9 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)......................... 10 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ............................ 11 Clock Output Additive Time Jitter (VCO Divider Not Used) .......................................................... 11 Clock Output Additive Time Jitter (VCO Divider Used) ..... 12 Serial Control Port—SPI Mode ................................................ 12 Serial Control Port—I2C Mode ................................................ 13 PD, SYNC, and RESET Pins ..................................................... 14 Serial Port Setup Pins: SP1, SP0 ............................................... 14 LD, STATUS, and REFMON Pins............................................ 14 Power Dissipation....................................................................... 15 Absolute Maximum Ratings.......................................................... 16 Thermal Resistance .................................................................... 16 ESD Caution................................................................................ 16 Pin Configuration and Function Descriptions........................... 17 Typical Performance Characteristics ........................................... 20 Terminology .................................................................................... 24 Detailed Block Diagram ................................................................ 25 Theory of Operation ...................................................................... 26 Operational Configurations...................................................... 26 Mode 1: Clock Distribution or External VCO < 1600 MHz .................................................. 26 Mode 2: High Frequency Clock Distribution— CLK or External VCO > 1600 MHz .................................... 28 Phase-Locked Loop (PLL) .................................................... 30 Configuration of the PLL ...................................................... 30 Phase Frequency Detector (PFD) ........................................ 30 Charge Pump (CP)................................................................. 30 PLL External Loop Filter....................................................... 31 PLL Reference Inputs............................................................. 31 Reference Switchover............................................................. 31 Reference Divider R............................................................... 32 VCO/VCXO Feedback Divider N: P, A, B, R ..................... 32 Digital Lock Detect (DLD) ................................................... 33 Analog Lock Detect (ALD)................................................... 34 Current Source Digital Lock Detect (CSDLD) .................. 34 External VCXO/VCO Clock Input (CLK/CLK) ................ 34 Holdover.................................................................................. 34 External/Manual Holdover Mode........................................ 35 Automatic/Internal Holdover Mode.................................... 35 Frequency Status Monitors ................................................... 37 Zero Delay Operation................................................................ 38 Clock Distribution ..................................................................... 39 Operation Modes ................................................................... 39 CLK Direct-to-LVPECL Outputs......................................... 39 Clock Frequency Division..................................................... 40 VCO Divider........................................................................... 40 Channel Dividers ................................................................... 40 Synchronizing the Outputs—SYNC Function ................... 42 LVPECL Output Drivers ....................................................... 43 CMOS Output Drivers .......................................................... 44 Reset Modes ................................................................................ 44 Power-On Reset...................................................................... 44 Hardware Reset via the RESET Pin ..................................... 44 Soft Reset via the Serial Port................................................. 44 Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port..................................... 44 Power-Down Modes .................................................................. 44 Chip Power-Down via PD .................................................... 44 PLL Power-Down................................................................... 45 Distribution Power-Down .................................................... 45 Individual Clock Output Power-Down............................... 45 Individual Clock Channel Power-Down............................. 45 |
Numéro de pièce similaire - AD9520-5BCPZ |
|
Description similaire - AD9520-5BCPZ |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |