AD9239BCPZ-210 datasheet(6/40 Pages) AD

No de pièce	AD9239BCPZ-210

Description	Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC

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AD9239

Rev. 0 | Page 6 of

40

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless

otherwise noted.

Table 4.

AD9239BCPZ-170

AD9239BCPZ-210

AD9239BCPZ-250

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK

Clock Rate

Full

170

100

210

100

250

100

MSPS

Clock Pulse Width High (tEH)

Full

2.65

2.9

2.15

2.4

1.8

2.0

ns

Clock Pulse Width Low (tEL)

Full

2.65

2.9

2.15

2.4

1.8

2.0

ns

DATA OUTPUT PARAMETERS

Data Output Period or UI

(DOUT + x, DOUT − x)

Full

1/(16 × fCLK)

sec

Data Output Duty Cycle

25°C

50

%

Data Valid Time

25°C

0.8

UI

PLL Lock Time (tLOCK)

25°C

4

μs

Wake-Up Time (Standby)

25°C

250

ns

Wake-Up Time (Power-Down)2

25°C

50

μs

Pipeline Latency

Full

40

CLK cycles

Data Rate per Channel (NRZ)

25°C

2.72

3.36

4.0

Gbps

Deterministic Jitter

25°C

10

ps max

Random Jitter

25°C

6

ps rms

Channel-to-Channel Bit Skew

25°C

0

sec

Channel-to-Channel Packet Skew3

25°C

+1

CLK cycles

Output Rise/Fall Time

25°C

50

ps

TERMINATION CHARACTERISTICS

Differential Termination Resistance

25°C

100

Ω

APERTURE

Aperture Delay (tA)

25°C

1.2

ns

Aperture Uncertainty (Jitter)

25°C

0.2

ps rms

OUT-OF-RANGE RECOVERY TIME

25°C

1

CLK cycles

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.

2 Receiver dependent.

3 See the

section.

Digital Start-Up Sequence

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