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TPS3818G33 Fiches technique(PDF) 3 Page - Texas Instruments |
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TPS3818G33 Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 16 page ELECTRICAL CHARACTERISTICS TPS3818 www.ti.com ......................................................................................................................................................... SBVS106A – MAY 2008 – REVISED AUGUST 2008 1.7V ≤ VDD ≤ 6.5V, RLRESET = 100kΩ, CLRESET = 50pF, over operating temperature range (TJ = –40°C to +125°C), unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –40°C < TJ < +125°C 1.7 6.5 VDD Input supply range V 0°C < TJ < +85°C 1.65 6.5 VDD = 3.3V, RESET not asserted 2.4 5.0 µA MR, RESET, CT open IDD Supply current (current into VDD pin) VDD = 6.5V, RESET not asserted 2.7 6.0 µA MR, RESET, CT open 1.3V ≤ VDD < 1.8V, IOL = 0.4mA 0.3 V VOL Low-level output voltage 1.8V ≤ VDD ≤ 6.5V, IOL = 1.0mA 0.4 V Power-up reset voltage(1) VOL (max) = 0.2V, IRESET = 15µA 0.8 V TPS3818G01 –2.0 ±1.0 +2.0 VIT ≤ 3.3V –1.5 ±0.5 +1.5 Negative-going VIT input threshold 3.3V < VIT ≤ 5.0V –2.0 ±1.0 +2.0 % accuracy VIT ≤ 3.3V –40°C < TJ < +85°C –1.25 ±0.5 +1.25 3.3V < VIT ≤ 5.0V –40°C < TJ < +85°C –1.5 ±0.5 +1.5 TPS3818G01 1.5 3.0 VHYS Hysteresis on VIT pin –40°C < TJ < +85°C 1.0 2.0 %VIT Fixed versions 1.0 2.5 RMR MR Internal pull-up resistance 70 90 k Ω TPS3818G01 VSENSE = VIT –25 25 nA Input current at ISENSE SENSE pin Fixed versions VSENSE = 6.5V 1.7 µA IOH RESET leakage current VRESET = 6.5V, RESET not asserted 300 nA CT pin VIN = 0V to VDD 5 Input capacitance, CIN pF any pin Other pins VIN = 0V to 6.5V 5 VIL MR logic low input 0 0.3 VDD V VIH MR logic high input 0.7 VDD VDD SENSE VIH = 1.05VIT, VIL = 0.95VIT 20 Input pulse width tw µs to RESET MR VIH = 0.7VDD, VIL = 0.3VDD 0.001 CT = Open 12 20 28 ms td RESET delay time(2) See Timing Diagram CT = VDD 180 300 420 ms CT pin (RESET delay time) comparator VCT 1.211 1.23 1.249 V threshold(3) CT pin (RESET delay time) charging RCT= 2MΩ (resistor between CT and ICT 190 220 250 nA current(3) GND) Propagation delay MR to RESET VIH = 0.7VDD, VIL = 0.3VDD 150 ns tpHL High to low level SENSE to RESET VIH = 1.05VIT, VIL = 0.95VIT 20 µs RESET delay θ JA Thermal resistance, junction-to-ambient 290 °C/W (1) The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15µs/V. (2) The delay time accuracy without external capacitor is the same as that of the TPS3808xxx. This specification is included here for TPS3808xxx device comparison. (3) The combined RESET delay time accuracy from VCT and ICT is ±15%. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TPS3818 |
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Description similaire - TPS3818G33 |
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