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H838776 Fiches technique(PDF) 77 Page - Renesas Technology Corp |
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H838776 Fiches technique(HTML) 77 Page - Renesas Technology Corp |
77 / 594 page Section 3 Exception Handling Rev. 1.00 Dec. 18, 2006 Page 55 of 568 REJ09B0348-0100 Section 3 Exception Handling Exception handling may be caused by a reset or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. • Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. |
Numéro de pièce similaire - H838776 |
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Description similaire - H838776 |
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