© 2006 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FIN324C Rev. 1.1.2

3

Pin Definitions

Pin

I/O Type

# Pins

Description of Signals

M/S

CMOS IN

1

Master/Slave Control Input:

The master is tied to the processor. The slave is tied to the display(s).

M/S=1 MASTER, M/S=0 SLAVE

/RES

CMOS IN

1

Reset and power-down signal

/RES=0: Resets and powers down all circuitry

/RES=1: Device enabled

/STBY

CMOS IN

1

Master standby signal

/STBY=0: Device powered down

/STBY=1: Device enabled

SLEW

CMOS IN

1

Slave output slew rate control

SLEW=1: Fast edge rate

SLEW=0: Slow edge rate

PAR/SPI

CMOS IN

1

Parallel / SPI display interface select

PAR/SPI=1: Parallel Interface

PAR/SPI=0: SPI Interface using STRB0 and WCLK0

CKSEL

CMOS IN

1

Master clock source select input.

CKSEL=1: STRB1 and WCLK1 Active

CKSEL=0: STRB0 and WCLK0 Active

DP[17:0]

CMOS I/O

18

Parallel data I/O.

I/O direction controlled by M/S pin and R/W internal state.

DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only)

DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only)

CNTL[5:0]

CMOS I/O

6

Parallel data I/O. I/O direction controlled by M/S pin

M/S=1: Inputs

M/S=0: Outputs

R/W

CMOS I/O

1

Read / Write input control or output signal.

M/S=1: Input

M/S=0: Output

Functional operation:

R/W=1: Read

R/W=0: Write

STRB0

STRB1

CMOS IN

2

Word latch or pixel clock input.

WCLK0

WCLK1

CMOS

OUT

2

Word latch or pixel clock output.

SCLK

SDAT

/CS

CMOS I/O

2

SPI mode signal pins.

The master SCLK input is shared with CNTL[5] when M/S=1 and PARI/SPI=0.

The master SDAT input is shared with CNTL[4] when M/S=1 and PARI/SPI=0.

The master /CS input is shared with STRB0 when M/S=1 and PAR/SPI=0.

The slave SCLK output is shared with DP[6] and CNTL[5] when M/S=0 and PAR/SPI=0.

The slave SDAT output is shared with DP[7] and CNTL[4] when M/S=0 and PAR/SPI=0.

The slave /CS output is shared with WCLK0 when M/S=0 and PAR/SPI=0.

CKS+

CKS-

Differential

Serial I/O

2

Serial clock differential signal

(1)

DS+

DS-

Differential

Serial I/O

2

Serial data differential signal

(1)

VDDP

Supply

1

Power supply for parallel I/O and internal circuitry.

VDDS

Supply

1

Power supply for serial I/O.

VDDA

Supply

1

Power supply for internal bit clock generator.

GND

Supply

1-3

Ground Pins:

BGA - C1 and D2; E3 is for supplier use only and must be tied to ground.

MLP - center pad; Pin 12 is for supplier use only and must be tied to ground.

Note

:

1.

Serial I/O signals are swapped on the slave so system traces do not have to cross between master and slave.