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STPC4EDBI Fiches technique(PDF) 6 Page - STMicroelectronics |
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STPC4EDBI Fiches technique(HTML) 6 Page - STMicroelectronics |
6 / 93 page GENERAL DESCRIPTION 6/93 Release 1.5 - January 29, 2002 or a 3 line flicker filter (primarily designed for Windows type displays). The fliker filter is optional and can be software disabled for use with large screen area’s of video. The Video output pipeline of the STPC Consumer- II interfaces directly to the internal digital TV encoder. It takes a 24 bit RGB non-interlaced pixel stream and converts to a multiplexed 4:2:2 YCrCb 8 bit output stream, the logic includes a progressive to interlaced scan converter and logic to insert appropriate CCIR656 timing reference codes into the output stream. It facilitates the high quality display of VGA or full screen video streams received via the Video input port to standard NTSC or PAL televisions. The digital PAL/NTSC encoder outputs interlaced or non-interlaced video in PAL-B,D,G,H,I PAL-N, PAL-M or NTSC-M standards and “NTSC- 4.43” is also possible. The four frame (for PAL) or 2 frame (for NTSC) burst sequences are internally generated, subcarrier generation being performed numerically with CKREF as reference. Rise and fall times of synchronisation tips and burst envelope are internally controlled according to the relevant ITU-R and SMPTE recommendations. Video output signals are directed to four analog output pins through internal D/A converters giving, simultaneous R,G,B and composite CVBS outputs. 1.4. MEMORY CONTROLLER The STPC handles the memory data (DATA) bus directly, controlling from 2 to 128 MBytes. The SDRAM controller supports accesses to the Memory Banks to/from the CPU (via the host), from the VMI, to/from the CRTC, to the VIDEO & to/from the GE. (Banks 0 to 3) which can be populated with either single or double sided 72-bit (4 bit parity) DIMMs. Parity is not supported. The SDRAM controller only supports 64 bit wide Memory Banks. Four Memory Banks (if DIMMS are used; Single sided or two double-sided DIMMs) are supported in the following configurations (see Table 1-1) The SDRAM Controller supports buffered or unbuffered SDRAM but not EDO or FPM modes. SDRAMs must support Full Page Mode Type access. The STPC Memory Controller provides various programmable SDRAM parameters to allow the SDRAM interface to be optimized for different processor bus speeds SDRAM speed grades and CAS Latency. 1.5. IDE INTERFACE An industry standard EIDE (ATA 2) controller is built into the STPC Consumer-II. The IDE port is capable of supporting a total of four devices. 1.6. POWER MANAGEMENT The STPC Consumer-II core is compliant with the Advanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal computers. The Power Management Unit module (PMU) controls the power consumption providing a comprehensive set of features that control the power usage and supports compliance with the United States Environmental Protection Agency's Energy Star Computer Program. The PMU provides following hardware structures to assist the software in managing the power consumption by the system. - System Activity Detection. - Three power down timers. - Doze timer for detecting lack of system activity for short durations. - Stand-by timer for detecting lack of system activity for medium durations - Suspend timer for detecting lack of system activity for long durations. - House-keeping activity detection. - House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand- by state. Table 1-1. Memory configurations Memory Bank size Number Organisa tion Device Size 1Mx64 4 1Mx16 16Mbits 2Mx64 8 2Mx8 4Mx64 16 4Mx4 4Mx64 4 2Mx16x2 64Mbits 8Mx64 8 4Mx8x2 16Mx64 16 8Mx4x2 4Mx64 4 1Mx16x4 8Mx64 8 2Mx8x4 32Mx64 16 4Mx4x4 16Mx64 8 2Mx16x2 128Mbits 32Mx64 16 4Mx8x4 Table 1-1. Memory configurations Memory Bank size Number Organisa tion Device Size |
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