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STPCCONSUMER-II Fiches technique(PDF) 5 Page - STMicroelectronics |
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STPCCONSUMER-II Fiches technique(HTML) 5 Page - STMicroelectronics |
5 / 93 page GENERAL DESCRIPTION Release 1.5 - January 29, 2002 5/93 1. GENERAL DESCRIPTION At the heart of the STPC Consumer-II is an advanced 64-bit x86 processor block. It includes a 64-bit SDRAM controller, advanced 64-bit accelerated graphics and video controller, a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus). The STPC Consumer-II has in addition, an EIDE Controller, I2C Interface, a Local Bus interface and a JTAG interface. 1.1. ARCHITECTURE The STPC Consumer-II makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buffer. This means a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional PCI bus. The 64-bit wide memory array provides the system with 528MB/s peak bandwidth. This allows for higher resolution screens and greater color depth. The ‘standard’ PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional functions such as communications ports are accessed by the STPC Consumer-II via internal ISA bus. The PCI bus is the main data communication link to the STPC Consumer-II chip. The STPC Consumer-II translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports generation of Configuration cycles on the PCI bus. The STPC Consumer-II, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devices. The STPC Consumer-II has two functional blocks sharing the same balls : The ISA / IPC / IDE block and the Local Bus / IDE block (see Table 3). Any board with the STPC Consumer-II should be built using only one of these two configurations. The IDE pins are dynamically multiplexed in each of the blocks in ISA mode only. Configuration is done by ‘strap options’. It is a set of pull-up or pull-down resistors on the memory data bus, checked on reset, which auto-configure the STPC Consumer-II. 1.2. GRAPHICS FEATURES Graphics functions are controlled through the on- chip SVGA controller and the monitor display is produced through the 2D graphics display engine. This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost. It performs limited graphics drawing operations which include hardware acceleration of text, bitblts, transparent blts and fills. The results of these operations change the contents of the on-screen or off- screen frame buffer areas of SDRAM memory. The frame buffer can occupy a space up to 4 Mbytes anywhere in the physical main memory. The graphics resolution supported is a maximum of 1280x1024 in 16M colors and 16M colors at 75Hz refresh rate, VGA and SVGA compatible. Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate above display resolution. 1.3. VIDEO FUNCTIONS The STPC Consumer-II provides several additional functions to handle MPEG or similar video streams. The Video Input Port accepts an encoded digital video stream in one of a number of industry standard formats, decodes it, optionally decimates it, and deposits it into an off screen area of the frame buffer. An interrupt request can be generated when an entire field or frame has been captured. The video output pipeline incorporates a video-scaler and color space converter function and provisions in the CRT controller to display a video window. While repainting the screen the CRT controller fetches both the video as well as the normal non-video frame buffer in two separate internal FIFOs. The video stream can be color-space converted (optionally) and smooth scaled. Smooth interpolative scaling in both horizontal and vertical direction are implemented. Color and Chroma key functions are also implemented to allow mixing video stream with non-video frame buffer. The video output passes directly to the RAMDAC for monitor output or through another optional color space converter (RGB to 4:2:2 YCrCb) to the programmable anti-flicker filter. The flicker filter is configured as either a two line filter with gamma correction (primarily designed for DOS type text) |
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