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FXL2SD106 Fiches technique(PDF) 10 Page - Fairchild Semiconductor |
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FXL2SD106 Fiches technique(HTML) 10 Page - Fairchild Semiconductor |
10 / 14 page ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FXL2SD106 Rev. 1.8.0 10 Figure 5. Active Output Rise Time and Dynamic Output Current High Figure 6. Active Output Fall Time and Dynamic Output Current Low trise 80% x VCCO 20% x VCCO IOHD ≈ (CL +CI/O) x = (CL +CI/O) x ∆VOUT ∆t VOH VOL VOUT Time (20% – 80%) x VCCO tRISE tfall 80% x VCCO 20% x VCCO VOL VOH VOUT Time IOLD ≈ (CL +CI/O) x = (CL +CI/O) x ∆VOUT ∆t (80% – 20%) x VCCO tFALL Figure 7. Maximum Data Rate Figure 8. Output Skew Time VCCI VCCI/2 VCCI/2 GND DATA IN tW Max. data rate, f = 1/tW VCCO Vmo tskew tskew Vmo GND DATA OUTPUT tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) VCCO Vmo Vmo GND DATA OUTPUT |
Numéro de pièce similaire - FXL2SD106 |
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Description similaire - FXL2SD106 |
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