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LFX1200EC-5FN900I Fiches technique(PDF) 8 Page - Lattice Semiconductor

No de pièce LFX1200EC-5FN900I
Description  ispXPGA Family
Download  115 Pages
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Fabricant  LATTICE [Lattice Semiconductor]
Site Internet  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFX1200EC-5FN900I Fiches technique(HTML) 8 Page - Lattice Semiconductor

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Lattice Semiconductor
ispXPGA Family Data Sheet
8
Figure 6. ispXPGA Wide Logic Generator
Configurable Sequential Element
There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in
implementing efficient pipelined applications with no utilization penalty. Each register can be configured as a latch
or D type flip-flop with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the
register’s D inputs. Feed-through signals in the architecture ensure that registers are efficiently utilized even if the
accompanying LUT is occupied.
Control Logic
The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the
various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX
with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or
complement form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common
4B
S2
4C
S1
4D
S0
COUT
WLGW0
WLGW1
WLGX0
WLGX1
WLGY0
WLGY1
WLGZ0
WLGZ1
4A
S3
SEL0
SEL1
SEL2
WIN2
WIN3
XIN2
XIN3
YIN2
YIN3
ZIN2
ZIN3
SEL3


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