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LFSC3GA40KLUTSEP1FF1020C Fiches technique(PDF) 10 Page - Lattice Semiconductor

No de pièce LFSC3GA40KLUTSEP1FF1020C
Description  LatticeSC/M Family Data Sheet
Download  237 Pages
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Fabricant  LATTICE [Lattice Semiconductor]
Site Internet  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFSC3GA40KLUTSEP1FF1020C Fiches technique(HTML) 10 Page - Lattice Semiconductor

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2-6
Architecture
Lattice Semiconductor
LatticeSC/M Family Data Sheet
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Routing
There are many resources provided in the LatticeSC devices to route signals individually or as busses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU)
resources. The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal
directions. All connections are buffered to ensure high-speed operation even with long high-fanout connections.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
sysCLOCK Network
The LatticeSC devices have three distinct clock networks for use in distributing high-performance clocks within the
device: primary clocks, secondary clocks and edge clocks. In addition to these dedicated clock networks, users are
free to route clocks within the device using the general purpose routing. Figure 2-4 shows the clock resources
available to each slice.
Figure 2-4. Slice Clock Selection
Primary Clock Sources
LatticeSC devices have a wide variety of primary clock sources available. Primary clocks sources consists of the
following:
• Primary clock input pins
• Edge clock input pins
• Two outputs per DLL
Logic
Ripple
RAM
ROM
LUT 4x8 or
MUX 2x1 x 8
2-bit Add x 4
SPR 16x2 x 4
DPR 16x2 x 2
ROM 16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
SPR 16x4 x 2
DPR 16x4 x 1
ROM 16x2 x 4
LUT 6x2 or
MUX 8x1 x 2
2-bit Counter x 4
SPR 16x8 x 1
ROM 16x4 x 2
LUT 7x1 or
MUX 16x1 x 1
2-bit Comp x 4
ROM 16x8 x1
Primary Clock
Secondary Clock
Routing
Clock to Slice
GND
12
6
Note: GND is available to switch off the network.


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