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LFSC3GA40KLUTSEP1F256C Fiches technique(PDF) 7 Page - Lattice Semiconductor

No de pièce LFSC3GA40KLUTSEP1F256C
Description  LatticeSC/M Family Data Sheet
Download  237 Pages
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Fabricant  LATTICE [Lattice Semiconductor]
Site Internet  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFSC3GA40KLUTSEP1F256C Fiches technique(HTML) 7 Page - Lattice Semiconductor

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2-3
Architecture
Lattice Semiconductor
LatticeSC/M Family Data Sheet
PFU Blocks
The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arith-
metic, Distributed RAM and Distributed ROM functions.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to implement 5, 6, 7 and 8 Input LUTs (LUT5, LUT6,
LUT7 and LUT8). There is control logic to perform set/reset functions (programmable as synchronous/asynchro-
nous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic
of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are seven outputs: six to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associ-
ated with each slice.
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
From
Routing
To
Routing
Slice 3
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D


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