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LFE220E-5F256C Fiches technique(PDF) 11 Page - Lattice Semiconductor |
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LFE220E-5F256C Fiches technique(HTML) 11 Page - Lattice Semiconductor |
11 / 386 page 2-8 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Delay Locked Loops (DLL) In addition to PLLs, the LatticeECP2/M family of devices has two DLLs per device. CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference input of the Phase Frequency Detector (PFD) input mux. The reference signal for the PFD can also be generated from the Delay Chain and CLKFB signals. The feedback input to the PFD is generated from the CLKFB pin, CLKI or from tapped signal from the Delay chain. The PFD produces a binary number proportional to the phase and frequency difference between the reference and feedback signals. This binary output of the PFD is fed into a Arithmetic Logic Unit (ALU). Based on these inputs, the ALU determines the correct digital control codes to send to the delay chain in order to better match the refer- ence and feedback signals. This digital code from the ALU is also transmitted via the Digital Control bus (DCNTL) bus to its associated DLLDELA delay block. The ALUHOLD input allows the user to suspend the ALU output at its current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus. The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with optional duty cycle correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK out- put signal is asserted when the DLL is locked. Figure 2-6 shows the DLL block diagram and Table 2-5 provides a description of the DLL inputs and outputs. The user can configure the DLL for many common functions such as time reference delay mode and clock injection removal mode. Lattice provides primitives in its design tools for these functions. For more information about the DLL, please see the list of additional technical documentation at the end of this data sheet. Figure 2-6. Delay Locked Loop Diagram (DLL) CLKOP CLKOS LOCK CLKFB CLKI ALUHOLD DCNTL UDDCNTL Phase Frequency Detector Delay3 Delay2 Delay1 Delay0 Delay4 Reference Feedback 9 ÷4 ÷2 ÷4 ÷2 RSTN (from routing or external pin) from CLKOP (DLL internal), from clock net (CLKOP) or from a user clock (pin or logic) Arithmetic Logic Unit Lock Detect Digital Control Output Delay Chain Output Muxes Duty Cycle 50% Duty Cycle 50% |
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