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LD39150DT12-R Fiches technique(PDF) 4 Page - STMicroelectronics |
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LD39150DT12-R Fiches technique(HTML) 4 Page - STMicroelectronics |
4 / 19 page Pin configuration LD39150 4/19 2 Pin configuration Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN) DFN8 (4x4 mm) DPAK PPAK Table 1. Pin description PlN N° SYMBOL NOTE DFN PPAK DPAK 85 VSENSE/N.C. For fixed versions: to be connected with LDO Output Voltage pins for DFN package and Not Connected on PPAK ADJ For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V 3, 4 2 1 VI LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a distance of not more than 0.5’’ from input pin. 6, 7 4 3 VO LDO Output Voltage pins, with minimum CO=2.2µF needed for stability (also refer to CO vs. ESR stability chart) 21 VINH Inhibit Input Voltage: ON MODE when VINH ≥ 2V, OFF MODE when VINH ≤ 0.3V (Do not leave floating, not internally pulled down/up) 1 3 2 GND Common ground 5 N.C. Not Connected |
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