List of Figures
Figure 1-1.
Stellaris
® 2000 Series High-Level Block Diagram ............................................................... 26
Figure 2-1.
CPU Block Diagram ......................................................................................................... 34
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 35
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 44
Figure 5-2.
Test Access Port State Machine ....................................................................................... 47
Figure 5-3.
IDCODE Register Format ................................................................................................. 52
Figure 5-4.
BYPASS Register Format ................................................................................................ 53
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 53
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 55
Figure 7-1.
Flash Block Diagram ...................................................................................................... 110
Figure 8-1.
GPIO Port Block Diagram ............................................................................................... 135
Figure 8-2.
GPIODATA Write Example ............................................................................................. 136
Figure 8-3.
GPIODATA Read Example ............................................................................................. 136
Figure 9-1.
GPTM Module Block Diagram ........................................................................................ 176
Figure 9-2.
16-Bit Input Edge Count Mode Example .......................................................................... 180
Figure 9-3.
16-Bit Input Edge Time Mode Example ........................................................................... 181
Figure 9-4.
16-Bit PWM Mode Example ............................................................................................ 182
Figure 10-1.
WDT Module Block Diagram .......................................................................................... 211
Figure 11-1.
UART Module Block Diagram ......................................................................................... 235
Figure 11-2.
UART Character Frame ................................................................................................. 236
Figure 11-3.
IrDA Data Modulation ..................................................................................................... 238
Figure 12-1.
SSI Module Block Diagram ............................................................................................. 275
Figure 12-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 278
Figure 12-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 278
Figure 12-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 279
Figure 12-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 279
Figure 12-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 280
Figure 12-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 281
Figure 12-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 281
Figure 12-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 282
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 283
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 284
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 284
Figure 13-1.
I2C Block Diagram ......................................................................................................... 312
Figure 13-2.
I2C Bus Configuration .................................................................................................... 313
Figure 13-3.
START and STOP Conditions ......................................................................................... 313
Figure 13-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 314
Figure 13-5.
R/S Bit in First Byte ........................................................................................................ 314
Figure 13-6.
Data Validity During Bit Transfer on the I2C Bus ............................................................... 314
Figure 13-7.
Master Single SEND ...................................................................................................... 317
Figure 13-8.
Master Single RECEIVE ................................................................................................. 318
Figure 13-9.
Master Burst SEND ....................................................................................................... 319
Figure 13-10. Master Burst RECEIVE .................................................................................................. 320
Figure 13-11. Master Burst RECEIVE after Burst SEND ........................................................................ 321
Figure 13-12. Master Burst SEND after Burst RECEIVE ........................................................................ 322
November 29, 2007
8
Preliminary
Table of Contents