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CAT24C03LI-3 Fiches technique(PDF) 5 Page - Catalyst Semiconductor |
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CAT24C03LI-3 Fiches technique(HTML) 5 Page - Catalyst Semiconductor |
5 / 18 page CAT24C03/05 5 Doc No. 1116, Rev. B © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Figure 3. Acknowledge Timing Figure 2. Slave Address Bits 1 8 9 START SCL FROM MASTER BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER) DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACK DELAY ( ≤ tAA) ACK SETUP ( ≥ tSU:DAT) START CONDITION STOP CONDITION SDA SCL Figure 1. START/STOP Conditions Figure 4. Bus Timing tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH 1 0 1 0 A2 A1 a8 R/W CAT24C05 1 0 1 0 A2 A1 A0 R/W CAT24C03 |
Numéro de pièce similaire - CAT24C03LI-3 |
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Description similaire - CAT24C03LI-3 |
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