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AD7492AR Fiches technique(PDF) 10 Page - Analog Devices |
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AD7492AR Fiches technique(HTML) 10 Page - Analog Devices |
10 / 16 page REV. 0 AD7492 –10– 100nF PARALLELED INTERFACE 2.5V 0V TO 2.5V 1nF 10 F 0.1 F 47 F AD7492 AVDD VDRIVE DVDD REF OUT DB0– DB9 (DB11) CS BUSY CONVST RD VIN C/ P ANALOG SUPPLY 2.7V–5.25V ++ PS/ FS Figure 5. Typical Connection Diagram ADC TRANSFER FUNCTION The output coding of the AD7492 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSB, etc.). The LSB size is = 2.5/4096 for the AD7492. The ideal transfer characteristic for the AD7492 is shown in Figure 6. 111...111 111...110 111...000 011...111 000...010 000...001 000...000 0V 1/2LSB +VREF –1LSB ANALOG INPUT 1LSB = VREF/4096 Figure 6. Transfer Characteristic for 12 Bits AC ACQUISITION TIME In ac applications it is recommended to always buffer analog input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the ADC. Large values of impedance at the VIN pin of the ADC will cause the THD to degrade at high input frequencies. Table I. Dynamic Performance Specifications Typical Amplifier Input SNR THD Current Buffers 500 kHz 500 kHz Consumption AD9631 69.5 80 17 mA AD797 69.6 81.6 8.2 mA DC Acquisition Time The ADC starts a new acquisition phase at the end of a conver- sion and ends it on the falling edge of the CONVST signal. At the end of conversion there is a settling time associated with the sampling circuit. This settling time lasts 120 ns. The analog signal on VIN is also being acquired during this settling time; therefore, the minimum acquisition time needed is 120 ns. Figure 7 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase. R3 represents the source impedance of a buffer amplifier or resistive network, R1 is an internal switch resistance, R2 is for bandwidth control, and C1 is the sampling capacitor. C2 is back-plate capacitance and switch parasitic capacitance. During the acquisition phase the sampling capacitor must be charged to within 0.5 LSB of its final value. R3 R1 125 VIN C1 22pF C2 8pF R2 636 Figure 7. Equivalent Analog Input Circuit ANALOG INPUT Figure 8 shows the equivalent circuit of the analog input struc- ture of the AD7492. The two diodes, D1 and D2, provide ESD protection for the analog inputs. The capacitor C3 is typically about 4 pF and can be primarily attributed to pin capacitance. The resistor R1 is an internal switch resistance. This resistor is typically about 125 Ω. The capacitor C1 is the sampling capaci- tor while R2 is used for bandwidth control. R1 125 VIN C1 22pF C2 8pF R2 636 D1 D2 C3 4pF VDD Figure 8. Equivalent Analog Input Circuit PARALLEL INTERFACE The parallel interface of the AD7492 is 12 bits wide. The output data buffers are activated when both CS and RD are logic low. At this point the contents of the data register are placed onto the data bus. Figure 9 shows the timing diagram for the parallel port. Figure 10 shows the timing diagram for the parallel port when CS and RD are tied permanently low. In this setup, once the BUSY line goes from high to low, the conversion process is completed. The data is available on the output bus slightly before the falling edge of BUSY. It is important to point out that the data bus cannot change state while the A/D is doing a conversion as this would have a detrimental effect on the conversion in progress. The data out lines will go three-state again when either the RD or CS line goes high. Thus the CS can be tied low permanently, leaving the RD line to control conversion result access. Please reference the VDRIVE section for output voltage levels. OPERATING MODES The AD7492 has two possible modes of operation depending on the state of the CONVST pulse at the end of a conversion, Mode 1 and Mode 2. Mode 1 (High-Speed Sampling) In this mode of operation the CONVST pulse is brought high before the end of conversion, i.e., before the BUSY goes low (see Figure 10). If the CONVST pin is brought from high to low while BUSY is high, the conversion is restarted. When operating in |
Numéro de pièce similaire - AD7492AR |
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Description similaire - AD7492AR |
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