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ADE7569ASTZF16-RL2 Fiches technique(PDF) 9 Page - Analog Devices |
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ADE7569ASTZF16-RL2 Fiches technique(HTML) 9 Page - Analog Devices |
9 / 136 page Preliminary Technical Data ADE7566/ADE7569 Rev. PrA | Page 9 of 136 TIMING SPECIFICATIONS AC inputs during testing are driven at VSWOUT − 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH minimum for Logic 1 and VIL maximum for Logic 0 as shown in Figure 2. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 2. CLOAD for all outputs = 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Clock Input (External Clock Driven XTAL1) Parameter 32.768 kHz External Crystal Parameter Description Min Typ Max Unit tCK XTAL1 period 30.52 μs tCKL XTAL1 width low 6.26 μs tCKH XTAL1 width high 6.26 μs tCKR XTAL1 rise time 9 ns tCKF XTAL1 fall time 9 ns 1/tCORE Core clock frequency1 0.032768 1.024 4.096 MHz 1 The ADE7566/ADE7569 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR. DVDD – 0.5V 0.45V 0.2DVDD + 0.9V TEST POINTS 0.2DVDD – 0.1V VLOAD – 0.1V VLOAD VLOAD + 0.1V TIMING REFERENCE POINTS VLOAD – 0.1V VLOAD VLOAD – 0.1V Figure 2. Timing Waveform Characteristics |
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