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AD1884AJCPZ-RL Fiches technique(PDF) 10 Page - Analog Devices |
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AD1884AJCPZ-RL Fiches technique(HTML) 10 Page - Analog Devices |
10 / 20 page Rev. 0 | Page 10 of 20 | March 2008 AD1884A Table 4. Pin Function Descriptions Mnemonic Pin No. I/O Description DIGITAL INTERFACE SDATA_OUT BIT_CLK SDATA_IN SYNC RESET 5 6 8 10 11 I I I/O I I Link Serial Data Output. AD1884A input stream. Clocked on both edges of the BIT_CLK. Link Bit Clock. 24.000 MHz serial data clock. Link Serial Data Input. AD1884A output stream clocked only on one edge of BIT_CLK. Link Frame Sync. Link Reset. AD1884A master hardware reset. DIGITAL I/O and EAPD GPIO_2 MIC_BIAS-E/GPIO_1 EAPD/GPIO_0 S/PDIF_OUT 30 31 47 48 I/O I/O I/O O General-Purpose Input/Output Pin. Digital signal used to control or sense external circuitry. Microphone Bias for Port E/General-Purpose Input/Output. Capable of high-Z, 1.65 V, and 2.86 V. Pin 31 shares functionality between MIC_BIAS-E (default) and GPIO_1. These functions are mutually exclusive and the MIC_BIAS function takes priority over the GPIO function. EAPD/General-Purpose Input/Output Pin. Pin 47 shares functionality between GPIO_0 and EAPD. These functions are mutually exclusive and the EAPD function takes priority over the GPIO function. By default, the pin is in a high-Z state. External resistors should be used to ensure the proper circuit state when this pin is in high-Z. Supports S/PDIF Output. JACK SENSE SENSE_A/SRC_B SENSE_B/SRC_A 13 34 I/O I/O Jack Sense A-D Input/Sense B Drive. Jack Sense E-F Input/Sense A Drive. ANALOG I/O PCBEEP PORT-E_L PORT-E_R PORT-F_L PORT-F_R CD_GND (PORT-F) PORT-B_L PORT-B_R PORT-C_L PORT-C_R MONO_OUT PORT-D_L PORT-D_R PORT-A_L PORT-A_R 12 14 15 16 17 19 21 22 23 24 32 35 36 39 41 LI LI, MIC, LO LI, MIC, LO LI, LO LI, LO I LI, MIC LI, MIC LI, MIC LI, MIC LO HP, LO HP, LO HP, LO HP, LO Monaural Input from System for Analog PCBeep. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. CD Audio Analog Ground Reference. Must be connected to AGND via a 0.1 μF capacitor if not in use as CD_GND. MUST always be ac-coupled. Front Panel Stereo MIC/Line-In. Front Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. FILTER/MIC_BIAS VREF _FLT MIC_BIAS-B MIC_BIAS-C MIC_BIAS_IN 5.0 V or 3.3 V 27 28 29 33 O O O I Voltage Reference Filter. Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24). Both MIC bias pins are capable of: High-Z, 0 V, 1.65 V, 3.7 V, and 3.9 V (with 5.0 V on Pin 33) High-Z, 0 V, 1.65 V, 2.86 V, and 3.0 V (with 3.3 V on Pin 33). Source Power for Microphone Bias Boost Circuitry. Connect this pin to 5.0 V via a low-pass filter. When connected this way, the AD1884A is capable of providing 3.9 V as a mic bias to all of the mic bias pins (except on Pin 31). If 5 V is not available, connect this pin to 3.3 V (AVDD) via a low-pass filter. The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving headphone load, MIC = input supports microphones with MIC bias and boost amplifier. |
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