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ST93C47AB1013TR Fiches technique(PDF) 6 Page - STMicroelectronics |
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ST93C47AB1013TR Fiches technique(HTML) 6 Page - STMicroelectronics |
6 / 13 page MEMORY ORGANIZATION The ST93C46 is organised as 128 bytes x 8 bits or 64 words x 16 bits. If the ORG input is left uncon- nected (or connected to VCC) the x16 organization is selected, when ORG is connected to Ground (VSS) the x8 organization is selected. When the ST93C46 is in standby mode, the ORG input should be unconnected or set to either VSS or VCC in order to get minimum power consumption. Any voltage between VSS and VCC applied to ORG may increase the standby current value. POWER-ON DATA PROTECTION During power-up, A Power On Reset sequence is run in order to reset all internal programming cir- cuitry and the device is set in the Write Disable mode. When VCC reaches its functional value, the device is properlyreset (in the Write Disable mode) and is ready to decode and execute an incoming instruction. INSTRUCTIONS The ST93C46 has seven instructions, as shown in Table 6. Each instruction is preceded by the rising edge of the signal applied on the S input (assuming that the clock C is low), followed by a ’1’ read on D input during the rising edge of the clock C. The op-codes of the instructions are made up of the 2 followingbits. Some instructions use only these first two bits, others use also the first two bits of the address to define the op-code. The op-code is followed by an address for the byte/word which is made up of six bits for the x16 organization or seven bits for the x8 organization. The ST93C46 is fabricated in CMOS technology and is therefore able to run from zero Hz (static input signals) up to the maximum ratings (specified in Table 5). Read The Read instruction (READ) outputs serial data on the Data Output (Q). When a READ instruction is received, the instruction and address are de- coded and the data from the memory is transferred into an output shiftregister. A dummy ’0’ bit is output first followed by the 8 bit byte or the 16 bit word with the MSB first. Output data changes are triggered by the Low to High transition of the Clock (C). The ST93C46 will automatically increment the address and will clock out the next byte/word as long as the Chip Select input (S) is held High. In this case the dummy ’0’ bit is NOT output between bytes/words and a continuous stream of data can be read. Erase/Write Enable and Disable The Erase/Write Enable instruction (EWEN) authorizes the following Erase/Write instructions to be executed, the Erase/Write Disable instruction (EWDS) freezes the execution of the following Erase/Write instructions. When power is first ap- plied to the ST93C46, Erase/Write is inhibited. When the EWEN instruction is executed, Write instructions remain enabled until an Erase/Write Disable instruction (EWDS) is executed or VCC falls below the power-on reset threshold. To protect the memory contents from accidental corruption, it is advisable to issue the EWDS instruction after every write cycle. The READ instruction is not affected by the EWEN or EWDS instructions. Instruction Description Op-Code x8 Org Address (ORG = 0) Data x16 Org Address (ORG = 1) Data READ Read Data from Memory 10 A6-A0 Q7-Q0 A5-A0 Q15-Q0 WRITE Write Data to Memory 01 A6-A0 D7-D0 A5-A0 D15-D0 EWEN Erase/Write Enable 00 11XXXXX 11XXXX EWDS Erase/Write Disable 00 00XXXXX 00XXXX ERASE Erase Byte or Word 11 A6-A0 A5-A0 ERAL Erase All Memory 00 10XXXXX 10XXXX WRAL Write All Memory with same Data 00 01XXXXX D7-D0 01XXXX D15-D0 Note: X = don’t care bit. Table 6. Instruction Set 6/13 ST93C46A/46C/46T, ST93C47C/47T |
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