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ST93C06CB1013TR Fiches technique(PDF) 6 Page - STMicroelectronics |
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ST93C06CB1013TR Fiches technique(HTML) 6 Page - STMicroelectronics |
6 / 15 page POWER-ON DATA PROTECTION In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit resets all internal programming circuitry and sets the device in the Write Disable mode. When VCC reaches its functional value, the device is properlyreset (in the Write Disable mode) and is ready to decode and execute an incoming instruction. A stable VCC must be applied before any logic signal. INSTRUCTIONS The ST93C06 has seven instructions, as shown in Table 6. The op-codes of the instructions are made up of 4 bits: some instructions use only the first two bits, others use all four bits to define the op-code. The op-code is followed by an address for the byte/word which is four bits long for the x16 organi- zation or five bits long for the x8 organization. Each instruction is preceded by the rising edge of the signal applied on the S input (assuming that clock C and data input D are low), followed by a first clock pulse which is ignored by the ST93C06 (optional clock pulse for the ST93C06C). The data input D is then sampled upon the following rising edges of the clock C untill a ’1’ is sampled and decoded by the ST93C06 as a Start bit. Even though the first clock pulse is ignored, it recom- mended to pull low the data input D during this first clock pulse in order to keep the timing upwardly compatible with other ST93Cxx devices. The ST93C06 is fabricated in CMOS technology and is therefore able to run from zero Hz (static input signals) up to the maximum ratings (specified in Table 5). Read The Read instruction (READ) outputs serial data on the Data Output (Q). When a READ instruction is received, the instruction and address are de- coded and the data from the memory is transferred into an output shiftregister. A dummy ’0’ bit is output first followed by the 8 bit byte or the 16 bit word with the MSB first. Output data changes are triggered by the Low to High transition of the Clock (C). The ST93C06 will automatically increment the address and will clock out the next byte/word as long as the Chip Select input (S) is held High. In this case the dummy ’0’ bit is NOT output between bytes/words and a continuous stream of data can be read. Erase/Write Enable and Disable The Erase/Write Enable instruction (EWEN) authorizes the following Erase/Write instructions to be executed, the Erase/Write Disable instruction (EWDS) disables the execution of the following Erase/Write instructions. When power is first ap- plied, the ST93C06 enters the Disable mode. When the Erase/Write Enable instruction (EWEN) is executed, Write instructions remain enabled until an Erase/Write Disable instruction (EWDS) is exe- cuted or if the Power-on reset circuit becomes active due to a reduced VCC. To protect the memory contents from accidental corruption, it is advisable to issue the EWDS instruction after every write cycle. The READ instruction is not affected by the EWEN or EWDS instructions. Erase The Erase instruction (ERASE) programs the ad- dressed memory byte or word bits to ’1’. Once the address is correctly decoded, the falling edge of the Chip Select input (S) triggers a self-timed erase cycle. Instruction Description Op-Code x8 Org Address (ORG = 0) Data x16 Org Address (ORG = 1) Data READ Read Data from Memory 10XX A4-A0 Q7-Q0 A3-A0 Q15-Q0 WRITE Write Data to Memory 01XX A4-A0 D7-D0 A3-A0 D15-D0 EWEN Erase/Write Enable 0011 XXXXX XXXX EWDS Erase/Write Disable 0000 XXXXX XXXX ERASE Erase Byte or Word 11XX A4-A0 A3-A0 ERAL Erase All Memory 0010 XXXXX XXXX WRAL Write All Memory with same Data 0001 XXXXX D7-D0 XXXX D15-D0 Note: X = don’t care bit. Table 6. Instruction Set 6/15 ST93C06, ST93C06C |
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