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ST90E158M9LVG0 Fiches technique(PDF) 6 Page - STMicroelectronics |
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ST90E158M9LVG0 Fiches technique(HTML) 6 Page - STMicroelectronics |
6 / 190 page 6/190 ST90158 - GENERAL DESCRIPTION 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST90158 and ST90135 microcontrollers are developed and manufactured by STMicroelectron- ics using a proprietary n-well CMOS process. Their performance derives from the use of a flexi- ble 256-register programming model for ultra-fast context switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-gener- ation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Inter- rupt and DMA controller, and the Memory Man- agement Unit. The MMU allows addressing of up to 4 Megabytes of program and data mapped into a single linear space. Four independent buses are controlled by the Core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit inter- rupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the core. This multiple bus architecture makes the ST9 fam- ily devices highly efficient for accessing on and off- chip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as ac- cumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. 1.1.2 Power Saving Modes To optimize performance versus power consump- tion, a range of operating modes can be dynami- cally selected. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). Slow Mode. Power consumption can be signifi- cantly reduced by running the CPU and the periph- erals at reduced clock speed using the CPU Pres- caler and CCU Clock Divider (PLL not used) or by using the CK_AF external clock. Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution un- til an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the CCU. In this mode, the power consumption of the device can be reduced by more than 95% (Low Power WFI). Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode. 1.1.3 system Clock A programmable PLL Clock Generator allows standard 3 to 5 MHz crystals to be used to obtain a large range of internal frequencies up to 24 MHz. 1.1.4 I/O Ports The I/O lines are grouped into up to nine 8-bit I/O Ports and can be configured on a bit basis to pro- vide timing, status signals, an address/data bus for interfacing to external memory, timer inputs and outputs, analog inputs, external interrupts and se- rial or parallel I/O. 9 |
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