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ST92F120JR6T Fiches technique(PDF) 10 Page - STMicroelectronics

No de pièce ST92F120JR6T
Description  8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
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ST92F120 - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the begin-
ning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (RW), and
Data signals are valid for memory transfers.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a
write cycle, data out is valid at the leading edge of
DS. During a read cycle, Data In must be valid pri-
or to the trailing edge of DS. When the ST9 ac-
cesses on-chip memory, DS is held high during
the whole memory cycle.
RESET. Reset (input, active low). The ST9 is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
RW. Read/Write (output, 3-state). Read/Write de-
termines the direction of data transfer for external
memory transactions. RW is low when writing to
external memory, and high for all other transac-
tions.
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal, or
an external source to the on-chip clock oscillator
and buffer. OSCIN is the input of the oscillator in-
verter and internal clock generator; OSCOUT is
the output of the oscillator inverter.
HW0SW1. When connected to VDD through a 1K
pull-up resistor, the software watchdog option is
selected. When connected to VSS through a 1K
pull-down resistor, the hardware watchdog option
is selected.
VPWO. This pin is the output line of the J1850 pe-
ripheral (JBLPD). It is available only on some de-
vices. On devices without JBLPD peripheral, this
pin must not be connected.
P0[7:0], P1[2:0] or P1[7:0]
(Input/Output, TTL or
CMOS compatible). 11 lines (TQFP64 devices) or
16 lines (PQFP100 devices) providing the external
memory interface for addressing 2K or 64 K bytes
of external memory.
P0[7:0], P1[2:0], P2[7:0], P3[7:4],
P4.[7:4],
P5[7:0], P6[5:2,0], P7[7:0]
I/O Port Lines (Input/
Output, TTL or CMOS compatible). I/O lines
grouped into I/O ports of 8 bits, bit programmable
under software control as general purpose I/O or
as alternate functions.
P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0]
Additional I/O Port Lines available on PQFP100
versions only.
AVDD. Analog VDD of the Analog to Digital Con-
verter (common for A/D 0 and A/D 1).
AVSS. Analog VSS of the Analog to Digital Con-
verter (common for A/D 0 and A/D 1).
VDD. Main Power Supply Voltage. Four pins are
available on PQFP100 versions, two on TQFP64
versions. The pins are internally connected.
VSS. Digital Circuit Ground. Four pins are availa-
ble on PQFP100 versions, two on TQFP64 ver-
sions. The pins are internally connected.
VPP. Power Supply Voltage for Flash test purpos-
es. This pin is bonded and must be kept to 0 in
user mode.
VREG. 3V regulator output.
1.2.1 Electromagnetic Compatibility (EMC)
To reduce the electromagnetic interference the fol-
lowing features have been implemented:
– A low power oscillator is included with a control-
led gain to reduce EMI and the power consump-
tion in Halt mode.
– Two or Four pairs of digital power supply pins
(VDD,VSS) are located on each side of the
PQFP100 package (2 pairs on TQFP64).
– Digital and analog power supplies are complete-
ly separated.
– Digital power supplies for internal logic and I/O
ports are separated internally.
– Internal decoupling capacitance is located be-
tween VDD and VSS.
Note: Each pair of digital VDD/VSS pins should be
externally connected by a 10
µF chemical pulling
capacitor and a 100 nF ceramic chip capacitor.
1.2.2 I/O Port Alternate Functions
Each pin of the I/O ports of the ST92F120 may as-
sume software programmable Alternate Functions
as shown in Section 1.3.
1.2.3 Termination of Unused Pins
The ST9 device is implemented using CMOS tech-
nology; therefore unused pins must be properly
terminated in order to avoid application reliability
problems. In fact, as shown in Figure 3, the stand-
ard input circuitry is based on the CMOS inverter
structure.
9


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