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ST72T512R4T1S Fiches technique(PDF) 6 Page - STMicroelectronics |
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ST72T512R4T1S Fiches technique(HTML) 6 Page - STMicroelectronics |
6 / 164 page ST72311R, ST72511R, ST72512R, ST72532R 6/164 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72311R, ST72511R, ST72512R and ST72532R devices are members of the ST7 mi- crocontroller family. They can be grouped as fol- lows: – ST725xxR devices are designed for mid-range applications with a CAN bus interface (Controller Area Network) – ST72311R devices target the same range of ap- plications but without CAN interface. All devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. Figure 1. Device Block Diagram 8-BIT CORE ALU OSC1 VPP CONTROL PROGRAM (16K - 60K Bytes) VSS RESE T PORT F PF7:0 (8-BIT) TIMER A BEEP PORT A RAM (1024, 2048 Bytes) PORT C 8-BIT ADC VDDA VSSA PORT B PB7:0 (8-BIT) PWM ART PORT E CAN PE7:0 (8-BIT) SCI TIMER B PA7:0 (8-BIT) PORT D PD7:0 (8-BIT) SPI PC7:0 (8-BIT) VDD EEPROM (256 Bytes) WATCHDOG TLI OSC LVD OSC2 MEMORY MCC/RTC 4 |
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