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ST9291J3 Fiches technique(PDF) 4 Page - STMicroelectronics |
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ST9291J3 Fiches technique(HTML) 4 Page - STMicroelectronics |
4 / 20 page The control of TV or Satellite receiver setting can be done by up to eight 8-bit PWM outputs, with a frequency maximum of 23,437Hz at 8-bit resolu- tion (INTCLK = 12MHz). Low resolutions with higher frequency operation can be programmed. In addition thereis a 3 channel Analog to Digital Con- verter with integral sample and hold, fast 5.75 µs con- version time and 6-bit guaranteed resolution. PIN DESCRIPTION VSYNC. Vertical Sync. Vertical video synchronisa- tion input to OSD. Positive or negative polarity. HSYNC. Horizontal Sync. Horizontal video syn- chronisation input to OSD. Positive or negative po- larity. PLLF. PLL Filter input. Filter input for the OSD for PLL feed-back. PLLR. PLL Resistor connection pin. For resistor connection to select the PLL gain adjust. RESET. Reset (input, active low). The ST9 is initial- ised by the Reset signal. With the deactivationof RE- SET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h. OSCIN, OSCOUT. Oscillator (input and output). These pins connect a parallel-resonant crystal GENERAL DESCRIPTION (Continued) (24MHz maximum), or an external source to the on-chip clock oscillator and buffer. OSCIN is the in- put of the oscillator inverter and internal clock gen- erator; OSCOUT is the output of the oscillator inverter. AVDD. Analog VDD of PLL. This pin must be tied to VDD externally to the ST9291. VDD. Main Power Supply Voltage (5V ±10%) VSS. Digital Circuit Ground. P0.0-P0.7, P2.0-P2.5, P3.0-P3.7, P4.0-P4.7, P5.0-P5.1 (J suffix) P0.0-P0.7, P1.0-P1.7, P2.0-P2.5, P3.0-P3.7, P4.0-P4.7, P5.0-P5.3 (N suffix) I/O Port Lines (In- put/Output, TTL or CMOS compatible). 32/42 lines grouped into I/O ports, bit programmable under program control as general purpose I/O or as Alter- nate functions (see next section). P4.0 - P4.7 are high voltage (12V) open drain out- puts. The voltage in open drain output mode for all other I/O bits must not exceed VDD. I/O Port Alternate Functions. Each pin of the I/O ports of the ST9291 may as- sume software programmable Alternative Func- tions as shown in the Pin Configuration Drawings. Table 1 shows the Functions allocated to each I/O Port pin. ® ST9291 4/20 |
Numéro de pièce similaire - ST9291J3 |
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Description similaire - ST9291J3 |
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