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ST9040 Fiches technique(PDF) 6 Page - STMicroelectronics |
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ST9040 Fiches technique(HTML) 6 Page - STMicroelectronics |
6 / 56 page Figure 3. ST9040 Block Diagram 1.2 PIN DESCRIPTION AS. Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the begin- ning of each memory cycle. The rising edge of AS indicates that address, Read/Write (R/W), and Data Memory signals are valid for program or data memory transfers. Under program control, AS can be placed in a high-impedance state along with Port 0 and Port 1, Data Strobe (DS) and R/W. DS. Data Strobe (output, active low, 3-state). Data Strobe provides the timing for data movement to or from Port 0 for each memory transfer. During a write cycle, data out is valid at the leading edge of DS. During a read cycle, Data In must be valid prior to the trailing edge of DS. When the ST9040 ac- cesses on-chip memory, DS is held high during the whole memory cycle. It can be placed in a high im- pedancestate alongwith Port 0, Port 1, AS and R/W. R/W. Read/Write (output, 3-state). Read/Write determines the direction of data transfer for exter- nal memory transactions. R/W is low when writing to external program or data memory, and high for all other transactions. It can be placed in a high im- pedancestate along with Port 0, Port 1, AS and DS. RESET. Reset (input, active low). The ST9 is initial- isedby the Reset signal. With the deactivationof RE- SET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h. INT0, INT7. External interrupts (input, active on ris- ing or falling edge). External interrupt inputs 0 and 7 respectively. INT0 channel may also be used for the timer watchdog interrupt. OSCIN, OSCOUT. Oscillator (input and output). These pins connect a parallel-resonant crystal (24MHz maximum), or an external source to the on-chip clock oscillator and buffer. OSCIN is the in- put of the oscillator inverter and internal clock gen- erator; OSCOUT is the output of the oscillator inverter. AVDD. AnalogVDD ofthe Analogto Digital Converter. AVSS. Analog VSS of the Analog to Digital Con- verter. Must be tied to VSS. VDD. Main Power Supply Voltage (5V ± 10%) VSS. Digital Circuit Ground. P0.0-P0.7, P1.0-P1.7, P2.0-P2.7 P3.0-P3.7, P4.0- P4.7, P5.0-P5.7, P7.0-P7.7 I/O Port Lines (In- put/Output, TTL or CMOS compatible). 56 lines grouped into I/O ports of 8 bits, bit programmable under program control as general purpose I/O or as alternate functions. 1.2.1 I/O Port Alternate Functions Each pin of the I/O ports of the ST9040 may as- sume software programmable Alternative Func- tions as shown in the Pin Configuration Drawings. Table 1-3 shows the Functions allocated to each I/O Port pins and a summary of packagesfor which they are available. CPU 16-Bit TIMER / WATCHDOG + SPI SCI WITH DMA I/O PORT 7 (S CI ) 8 256 Bytes REGISTER FILE 2 x 16-bi t TIME R WITH DMA I/O PORT 3 ( TIMERS ) 8 I/O PORT 0 (Address/Data ) 8 I/O PORT 1 ( Address ) 8 512 Bytes EEPROM 256 Bytes RAM 16 k Bytes ROM I/O PORT 2 ( SPI ) 8 I/O PORT 4 ( Analog Inputs ) 8 A/ D CONVERTER I/O PORT 5 WITH HANDSHAKE 8 MEMORY BUS REGISTER BUS VR001385 IN T0 INT7 AV DD AV SS ® ST9040 6/56 |
Numéro de pièce similaire - ST9040 |
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Description similaire - ST9040 |
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