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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST63E142D1 Fiches technique(PDF) 9 Page - STMicroelectronics |
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ST63E142D1 Fiches technique(HTML) 9 Page - STMicroelectronics |
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9 / 86 page  PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection. OSCin, OSCout. These pins are internally con- nected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the cor- rect operation of the MCU with various stabil- ity/cost trade-offs. The OSCin pin is the input pin, the OSCout pin is the output pin. RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. TEST. The TEST pin must be held at VSS for nor- mal operation. PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input or as an output under software control of the data direction register. Port A has an open-drain (12V drive) output configuration with direct LED driving capability (30mA, 1V). PB2-PB3, PB5-PB7. These lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resis- tor or as an output under software control of the data direction register. PB2-PB3 have a push-pull configuration in output mode while PB5-PB7 are open-drain (5V drive). PB2 and PB3 lines are connected to the VSYNC and HSYNC control signals of the OSD cell; to pro- vide the right signals to the OSD these I/O lines should be programmed in input mode and the user can read “on the fly” the state of VSYNC and HSYNC signals. PB2 is also connected with the VSYNC Interrupt. The active polarity of VSYNC In- terrupt signal is software controlled. The active po- larity of these synchronization input pins to the OSD macrocell can be selected by the user as ROM mask option. If the device is specified to have negative logic inputs, then when these signals are low the OSD oscillator stops. If the device is speci- fied to have positive logic inputs, then when these signals are high the OSD oscillator stops. PB5, PB6 and PB7 lines, when in output modes, are “ANDed” with the SPI control signals. PB5 is connected with the SPI clock signal (SCL), PB6 with the SPI data signal (SDA) while PB7 is con- nected with SPI enable signal (SEN). PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direc- tion register. PC0-PC2, PC4 have a push-pull con- figuration in output mode while PC3, PC5-PC7 (OSD signals) are open-drain (5V drive). PC3, PC5 , PC6 and PC7 lines when in output mode are “ANDed” with the character and blank signals of the OSD cell. PC3 is connected with the OSD BLANK signal, PC5, PC6 and PC7 with the OSD R, G and B signals. The active polarity of these sig- nals can be selected by the user as ROM mask op- tion. PC2 is also used as TV set ON-OFF switch (5V drive). DA0-DA3. These pins are the four PWM D/A out- puts (with 32kHz repetition) of the 6-bit on-chip D/A converters. The PWM function can be disabled by software and these lines can be used as general purpose open-drain outputs (12V drive). IRIN. This pin is the external NMI of the MCU. OUT1. This pin is the 62.5kHz output specially suited to drive multi-standard chroma processors. This function can be disabled by software and the pin can be used as general purpose open-drain output (12V drive). BSW0-BSW3. These output pins can be used to select up to 4 tuning bands. These lines are config- ured as open-drain outputs (12V drive). KBY0-KBY2. These pins are input only and can be used for keyboard scan. They have CMOS thresh- old levels with Schmitt Trigger and on-chip 100k Ω pull-up resistors. AFC. This is the input of the on-chip 10 level com- parator that can be used to implement the AFC function. This pin is an high impedance input able to withstand signals with a peak amplitude up to 12V. OSDOSCin, OSDOSCout. These are the On Screen Display oscillator terminals. An oscillation capacitor and coil network have to be connected to provide the right signal to the OSD. VS. This is the output pin of the on-chip 14-bit volt- age synthesis tuning cell (VS). The tuning signal present at this pin gives an approximate resolution of 40kHz per step over the UHF band. This line is a push-pull output with standard drive (ST63140, ST63156 only). ® ST63140,142,126,156 5/82 |
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Description similaire - ST63E142D1 |
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