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ST40RA Fiches technique(PDF) 7 Page - STMicroelectronics |
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ST40RA Fiches technique(HTML) 7 Page - STMicroelectronics |
7 / 94 page 4 Architecture ST40RA 7/94 STMicroelectronics ADCS 7260755H 4 Architecture 4.1 Overview The ST40RA combines an SH-4, 32-bit microprocessor with a wide range of interfaces to external peripherals. This section briefly describes each of the features of the ST40RA. 4.2 ST40 system 4.2.1 SuperH ST40 SH-4 core Figure 1 illustrates the system architecture of the ST40 SH-4 core. The following section briefly describes the features and performance of the core. Central processing unit The central processing unit is built around a 32-bit RISC, two-way superscalar architecture. Operating at 166 MHz it runs with high code density using fixed length 16-bit instructions. It has a load/store architecture, delayed branch instruction capability and an on-chip multiplier. It uses a five-stage pipeline. Figure 1: ST40 SH-4 core architecture CPU UBC FPU ICache 8 Kbytes ITLB UTLB Cache and TLB controller DCache 16 Kbytes Lower 32-bit data Lower 32-bit data |
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