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INPUT RESISTANCE

IN

Input

Signal

f=

1

2

Z C

p

i

i

(1)

f

=

c

1

2

Z C

p

i

i

–3dB

(2)

C =

i

1

2

Z f

p

i

c

(3)

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

For design purposes, the input network (discussed in the next section) should be designed assuming an input

impedance of 8 k

Ω, which is the absolute minimum input impedance of the TPA3122D2. At the higher gain

settings, the input impedance could increase as high as 72 k

Ω

Table 1. Gain Setting

AMPLIFIER GAIN (dB)

INPUT IMPEDANCE (k

Ω)

GAIN1

GAIN0

TYPICAL

TYPICAL

0

0

20

60

0

1

26

30

1

0

32

15

1

1

36

9

Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 k

Ω ±20%, to

the largest value, 60 k

Ω ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or

cutoff frequency may change when changing gain steps.

In the typical application, an input capacitor

high-pass filter with the corner frequency determined in Equation 2.

reconfigured as Equation 3.

the leakage path from the input source through the input network

leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially

Copyright © 2007, Texas Instruments Incorporated

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