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ST14C02C-S43 Fiches technique(PDF) 5 Page - STMicroelectronics

No de pièce ST14C02C-S43
Description  Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM
Download  12 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST14C02C-S43 Fiches technique(HTML) 5 Page - STMicroelectronics

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ST14C02C
Figure 6. Write Mode Sequences
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
AI01941
DATA IN N
ACK
ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
period the receiver pulls the SDA bus low to ac-
knowledge the receipt of the 8 data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change
only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW bit.
The seven most significant bits of the Device Se-
lect Code are the Device Type Identifier, according
to the I2C bus definition. For the memory device,
the seven bits are fixed at 1010000b (A0h), as
shown in Table 4.
The 8th bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-
responding memory gives an acknowledgment on
the SDA bus during the 9th bit time.
Write Operations
The Multibyte Write mode is selected when the
MODE pin is at VIH, and the Page Write mode is
selected when MODE pin is at VIL. The MODE pin
may be driven dynamically to CMOS input levels.
Following a START condition, the master sends a
Device Select Code with the RW bit reset to ‘0’.
The memory device acknowledges this, and waits
for a byte address. The 8-bit byte address allows
access within a 256-byte memory address-space.
After receipt of the byte address, the device again
responds with an acknowledge bit.
Byte Write
In the Byte Write mode, the master sends one data
byte, which is acknowledged by the memory, as
shown in Figure 6. The master then terminates the
transfer by generating a STOP condition. The
Write mode is independent of the state of the
MODE pin, as shown in Table 5, which could be
left floating if only this mode is to be used. Howev-
er this is not a recommended operating mode, as
this pin has to be connected to either VIH or VIL to
minimize the stand-by current.
Multibyte Write
For the Multibyte Write mode, the MODE pin must
be held at VIH, as shown in Table 5. The Multibyte
Write mode can be started from any address in the
memory. The master sends one, two, three or four
bytes of data, which are each acknowledged by
the memory. The transfer is terminated by the
master generating a STOP condition. The maxi-
mum duration of the write cycle is tW=10 ms (as
shown in Table 8), except when bytes span across
two rows. (That is, when they have different values
for the 6 most significant address bits, A7-A2). The
programming time is then doubled to a maximum
of 20 ms. Writing more than four bytes in the Multi-


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