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ST16-19RFRDCS Fiches technique(PDF) 9 Page - STMicroelectronics |
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ST16-19RFRDCS Fiches technique(HTML) 9 Page - STMicroelectronics |
9 / 21 page 3/15 FSD_CHIPSET_B/0104VP2 ST16-19RFRDCS 1.3.3 Write access chronogram FPGA write access chronogram, for transmission FIFO or control register: Figure 1 : FPGA write access chronogram In figure1, two types of access are shown. The first one is a Control register access (Mic_Ctrl_Data = ’1’) and the second one is a FIFO access (Mic_Ctrl_Data = ’0’). 1.3.4 Read access chronogram FPGA read access chronogram, for reception FIFO or status register: Figure 2 FPGA read acces chronogram In the figure 2, prior to sending data the FPGA takes the Rx_IRQ_EOF line low to indicate to the MCU that the data can be recuperated. Data writing Control register writing t4 t3 Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_fifo_empty Tx_start t1 t2 Acquisition of the next bytes, except the last one Acquisition of the first byte t6 t4 t3 Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_fifo_empty Tx_start t1 t2 t0 t5 |
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