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KMPC860DTZQ50D4 Fiches technique(PDF) 6 Page - Freescale Semiconductor, Inc |
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KMPC860DTZQ50D4 Fiches technique(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 80 page MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 6 Freescale Semiconductor Features — Allows dynamic changes — Can be internally connected to six serial channels (four SCCs and two SMCs) • Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on the MPC860 or the MC68360 • PCMCIA interface — Master (socket) interface, release 2.1 compliant — Supports two independent PCMCIA sockets — Supports eight memory or I/O windows • Low power support — Full on—all units fully powered — Doze—core functional units disabled except time base decrementer, PLL, memory controller, RTC, and CPM in low-power standby — Sleep—all units disabled except RTC and PIT, PLL active for fast wake up — Deep sleep—all units disabled including PLL except RTC and PIT — Power down mode—all units powered down except PLL, RTC, PIT, time base, and decrementer • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = ≠ <> — Each watchpoint can generate a break-point internally. • 3.3-V operation with 5-V TTL compatibility except EXTAL and EXTCLK • 357-pin ball grid array (BGA) package |
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Description similaire - KMPC860DTZQ50D4 |
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