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M74HC175M1R Fiches technique(PDF) 1 Page - STMicroelectronics |
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M74HC175M1R Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 11 page M54HC175 M74HC175 October 1992 QUAD D-TYPE FLIP-FLOP WITH CLEAR B1R (Plastic Package) ORDER CODES : M54HC175F1R M74HC175M1R M74HC175B1R M74HC175C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection DESCRIPTION . HIGH SPEED tPD = 13 ns (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE |IOH|= IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS175 The M54/74HC175 is a high speed CMOS QUAD D- TYPE FLIP-FLOP WITH CLEAR fabricated in sili- con gate CMOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These four flip-flops are controlled by a clock input (CLOCK) and a clear input (CLEAR). The informa- tion data applied to the D inputs (1D to 4D) are trans- fered to the outputs (1Q to 4Q and 1Q to 4Q) on the positive-going edge of the clock pulse. The reset function is accomplished when the clear input is taken low and all Q outputs are kept low regardless of other input conditions. All inputs are equipped with protection circuits against static discharge and transient excess voltage. 1/11 |
Numéro de pièce similaire - M74HC175M1R |
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