14.1
Block Diagram ........................................................................................................................ 331
14.2
Functional Description ............................................................................................................. 331
14.2.1 Bit Rate Generation ................................................................................................................. 332
14.2.2 FIFO Operation ....................................................................................................................... 332
14.2.3 Interrupts ................................................................................................................................ 332
14.2.4 Frame Formats ....................................................................................................................... 333
14.3
Initialization and Configuration ................................................................................................. 340
14.4
Register Map .......................................................................................................................... 341
14.5
Register Descriptions .............................................................................................................. 342
15
Inter-Integrated Circuit (I
2C) Interface ............................................................................ 366
15.1
Block Diagram ........................................................................................................................ 366
15.2
Functional Description ............................................................................................................. 366
15.2.1 I
2C Bus Functional Overview .................................................................................................... 367
15.2.2 Available Speed Modes ........................................................................................................... 369
15.2.3 Interrupts ................................................................................................................................ 370
15.2.4 Loopback Operation ................................................................................................................ 370
15.2.5 Command Sequence Flow Charts ............................................................................................ 371
15.3
Initialization and Configuration ................................................................................................. 377
15.4
I
2C Register Map ..................................................................................................................... 378
15.5
Register Descriptions (I
2C Master) ........................................................................................... 379
15.6
Register Descriptions (I2C Slave) ............................................................................................. 392
16
CAN ................................................................................................................................... 401
16.1
Controller Area Network Overview ............................................................................................ 401
16.2
Controller Area Network Features ............................................................................................ 401
16.3
Controller Area Network Block Diagram .................................................................................... 402
16.4
Controller Area Network Functional Description ......................................................................... 403
16.4.1 Initialization ............................................................................................................................. 403
16.4.2 Operation ............................................................................................................................... 404
16.4.3 Transmitting Message Objects ................................................................................................. 404
16.4.4 Configuring a Transmit Message Object .................................................................................... 404
16.4.5 Updating a Transmit Message Object ....................................................................................... 405
16.4.6 Accepting Received Message Objects ...................................................................................... 405
16.4.7 Receiving a Data Frame .......................................................................................................... 406
16.4.8 Receiving a Remote Frame ...................................................................................................... 406
16.4.9 Receive/Transmit Priority ......................................................................................................... 406
16.4.10 Configuring a Receive Message Object .................................................................................... 406
16.4.11 Handling of Received Message Objects .................................................................................... 407
16.4.12 Handling of Interrupts .............................................................................................................. 407
16.4.13 Bit Timing Configuration Error Considerations ........................................................................... 408
16.4.14 Bit Time and Bit Rate ............................................................................................................... 408
16.4.15 Calculating the Bit Timing Parameters ...................................................................................... 410
16.5
Controller Area Network Register Map ...................................................................................... 412
16.6
Register Descriptions .............................................................................................................. 414
17
Analog Comparators ....................................................................................................... 445
17.1
Block Diagram ........................................................................................................................ 446
17.2
Functional Description ............................................................................................................. 446
17.2.1 Internal Reference Programming .............................................................................................. 448
June 04, 2007
6
Preliminary
Table of Contents