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74ALVTH16374VRE4 Fiches technique(PDF) 8 Page - Texas Instruments |
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74ALVTH16374VRE4 Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 21 page www.ti.com Timing Requirements Timing Requirements SN54ALVTH16374,, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES068G – JUNE 1996 – REVISED NOVEMBER 2006 over recommended operating free-air temperature range V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) SN54ALVTH16374(1) SN74ALVTH16374 UNIT MIN MAX MIN MAX fclock Clock frequency 150 150 MHz tw Pulse duration, CLK high or low 1.5 1.5 ns Data high 1.1 1 tsu Setup time, data before CLK ↑ ns Data low 1.4 1.3 Data high 0.6 0.5 th Hold time, data after CLK ↑ ns Data low 0.9 0.8 (1) Product preview over recommended operating free-air temperature range V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) SN54ALVTH16374(1) SN74ALVTH16374 UNIT MIN MAX MIN MAX fclock Clock frequency 25 250 MHz tw Pulse duration, CLK high or low 1.5 1.5 ns Data high 1.1 1 tsu Setup time, data before CLK ↑ ns Data low 1.6 1.5 Data high 0.6 0.5 th Hold time, data after CLK ↑ ns Data low 1.1 1 (1) Product preview 8 Submit Documentation Feedback |
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