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M48Z02 Fiches technique(PDF) 3 Page - STMicroelectronics |
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M48Z02 Fiches technique(HTML) 3 Page - STMicroelectronics |
3 / 12 page AI01019 5V OUT CL = 100pF CL includes JIG capacitance 1.8k Ω DEVICE UNDER TEST 1k Ω Figure 4. AC Testing Load Circuit Input Rise and Fall Times ≤ 5ns Input Pulse Voltages 0V to 3V Input and Output Timing Ref. Voltages 1.5V Note that Output Hi-Z is defined as the point where data is no longer driven. Table 4. AC Measurement Conditions AI01255 LITHIUM CELL VPFD VCC VSS VOLTAGE SENSE AND SWITCHING CIRCUITRY 2K x 8 SRAM ARRAY A0-A10 DQ0-DQ7 E W G POWER Figure 3. Block Diagram READ MODE The M48Z02/12 is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through ac- cess of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address In- puts are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. 3/12 M48Z02, M48Z12 |
Numéro de pièce similaire - M48Z02 |
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Description similaire - M48Z02 |
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