TPIC5223L

2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL

POWER DMOS ARRAY

SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

1

POST OFFICE BOX 655303

description

The TPIC5223L is a monolithic gate-protected logic-level power DMOS array that consists of two electrically

isolated independent N-channel enhancement-mode DMOS transistors. Each transistor features integrated

occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body

model of a 100-pF capacitor in series with a 1.5-k

Ω resistor.

The TPIC5223L is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized

for operation over the case temperature of – 40

°C to 125°C.

schematic

D1

Z1

DRAIN1

GATE1

SOURCE1

Q1

7

8

D2

Z2

DRAIN2

GATE2

SOURCE2

Q2

3

4

2

GND

1

6

ZC1b

ZC1a

ZC2b

ZC2a

NOTE A: For correct operation, no terminal may be taken below GND.

Copyright

© 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

2

3

4

8

7

6

5

GND

SOURCE1

GATE2

DRAIN2

DRAIN1

GATE1

SOURCE2

NC

D PACKAGE

(TOP VIEW)

NC – No internal connection