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M27V800-150B1TR Fiches technique(PDF) 3 Page - STMicroelectronics |
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M27V800-150B1TR Fiches technique(HTML) 3 Page - STMicroelectronics |
3 / 16 page 3/16 M27V800 The M27V800 operates in the read mode with a supply voltage as low as 3V. The decrease in op- erating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. A new pattern can then be written rapidly to the device by following the programming proce- dure. For applications where the content is programmed only one time and erasure is not required, the M27V800 is offered in PDIP42, SO44 and PLCC44 package. DEVICE OPERATION The operating modes of the M27V800 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for VPP and 12V on A9 for the Electronic Signature. Read Mode The M27V800 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTEVPP pin. When BYTEVPP is at VIH the Word-wide organisation is selected and the Q15A–1 pin is used for Q15 Data Output. When the BYTEVPP pin is at VIL the Byte-wide or- ganisation is selected and the Q15A–1 pin is used for the Address Input A–1. When the memory is logically regarded as 16 bit wide, but read in the Byte-wide organisation, then with A–1 at VIL the lower 8 bits of the 16 bit data are selected and with A–1 at VIH the upper 8 bits of the 16 bit data are selected. The M27V800 has two control functions, both of which must be logically active in order to obtain data at the outputs. In addition the Word-wide or Byte-wide organisation must be selected. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins independent of device selection. Assuming that the addresses are stable, the ad- dress access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the ad- dresses have been stable for at least tAVQV-tGLQV. Table 3. Operating Modes Note: X = VIH or VIL,VID = 12V ± 0.5V. Table 4. Electronic Signature Note: Outputs Q8-Q15 are set to ’0’. Mode E G BYTEVPP A9 Q0-Q7 Q8-Q14 Q15A–1 Read Word-wide VIL VIL VIH X Data Out Data Out Data Out Read Byte-wide Upper VIL VIL VIL X Data Out Hi-Z VIH Read Byte-wide Lower VIL VIL VIL X Data Out Hi-Z VIL Output Disable VIL VIH X X Hi-Z Hi-Z Hi-Z Program VIL Pulse VIH VPP X Data In Data In Data In Verify VIH VIL VPP X Data Out Data Out Data Out Program Inhibit VIH VIH VPP X Hi-Z Hi-Z Hi-Z Standby VIH X X X Hi-Z Hi-Z Hi-Z Electronic Signature VIL VIL VIH VID Codes Codes Code Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer’s Code VIL 001 000 00 20h Device Code VIH 101 100 10 B2h |
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