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TPS2490DGSRG4 Fiches technique(PDF) 10 Page - Texas Instruments |
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TPS2490DGSRG4 Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 20 page www.ti.com V PROG + P LIM 10 I LIM P LIM t T J(MAX) * TS(MAX) R q JC(MAX) TPS2490 TPS2491 SLVS503 – NOVEMBER 2003 where PLIM is the desired power limit of M1 and ILIM is the current limit setpoint (see SENSE). PLIM is determined by the desired thermal stress on M1: where TJ(MAX) is the maximum desired transient junction temperature of M1 and TS(MAX) is the maximum case temperature prior to a start or restart. VPROG is used in conjunction with VDS to compute the (scaled) current, ID_ALLOWED, by the constant power engine. ID_ALLOWED is compared by the gate amplifier to the actual ID, and used to generate a gate drive. If ID < ID_ALLOWED, the amplifier turns the gate of M1 full on because there is no overload condition; otherwise GATE is regulated to maintain the ID = ID_ALLOWED relationship. A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 12 to look like a ramp. PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2490 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-k Ω resistor. TIMER: An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the fault-time for both versions and the restart interval for the TPS2491. The timer charges at 25 µA whenever the TPS2490/91 is in power limit or current limit and discharges at 2.5 µA otherwise. The charge-to-discharge current ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER reaches 4 V, the TPS2490 pulls GATE to ground, latch off, and discharge CT. The TPS2491 pulls GATE to ground and attempt a restart (re-enable GATE) after a timing sequence consisting of discharging CT down to 1 V followed by 15 more charge and discharge cycles. The TPS2490 can be reset by either cycling the EN pin or the UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin should be tied to ground if this feature is not used. PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG goes open-drain (high voltage with a pull-up) after VDS of M1 has fallen to about 1.25 V and a 9 ms deglitch time period has elapsed. PG is false (low or low resistance to ground) whenever EN is false, VDS of M1 is above 2.5 V, or UVLO is active. PG can also be viewed as having an input and output voltage monitor function. The 9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (low) such as a momentary overload or input voltage step. VPG voltage can be greater than VVCC because it’s ESD protection is only with respect to ground. GND: This pin is connected to system ground. 10 |
Numéro de pièce similaire - TPS2490DGSRG4 |
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Description similaire - TPS2490DGSRG4 |
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