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TMP320C6713GDPA225 Fiches technique(PDF) 11 Page - Texas Instruments

No de pièce TMP320C6713GDPA225
Description  FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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TMS320C6713
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
description
The TMS320C67x
t DSPs (including the TMS320C6713 device) compose the floating-point DSP generation
in the TMS320C6000
t DSP platform. The C6713 device is based on the high-performance, advanced
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an
excellent choice for multichannel and multifunction applications.
Operating at 225 MHz, the C6713 delivers up to 1350 million floating-point operations per second (MFLOPS),
1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million
multiply-accumulate operations per second (MMACS).
The C6713 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte
2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-Byte memory space that is
shared between program and data space. 64K Bytes of the 256K Bytes in L2 memory can be configured as
mapped memory, cache, or combinations of the two. The remaining 192K Bytes in L2 serves as mapped SRAM.
The C6713 has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two
Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated
General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a
glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous
peripherals.
The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP
has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports
time-division multiplexing on each pin from 2 to 32 time slots. The C6713 has sufficient bandwidth to support
all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and
received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips
Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430
encoded data channels simultaneously, with a single RAM containing the full implementation of user data and
channel status fields.
The McASP also provides extensive error-checking and recovery features, such as the bad clock detection
circuit for each high-frequency master clock which verifies that the master clock is within a programmed
frequency range.
The two I2C ports on the TMS320C6713 allow the DSP to easily control peripheral devices and communicate
with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The TMS320C6713 device has two bootmodes: from the HPI or from external asynchronous ROM. For more
detailed information, see the bootmode section of this data sheet.
The TMS320C67x DSP generation is supported by the TI eXpressDSP
t set of industry benchmark
development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio
t Integrated
Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS
t
kernel.
TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments.
† Throughout the remainder of this document, the TMS320C6713 shall be referred to as C6713 or 13.


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