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ADCS9888CVH-205 Fiches technique(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce ADCS9888CVH-205
Description  205/170/140 MSPS Video Analog Front End
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADCS9888CVH-205 Fiches technique(HTML) 6 Page - National Semiconductor (TI)

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Pin Descriptions (Continued)
Pin
Label
Type
Description
Data Clock Output
123
DATACK
Digital
Output
Data Output Clock. Complementary data clocks are provided so that output
data and HSOUT can be synchronously captured by external logic or
memory devices. The clock outputs are synchronous with the internal pixel
sample clock. As the sampling phase is adjusted, the DATACK, data, and
HSOUT signals all shift together with the sampling interval. When the chip
is in power down or seek mode, the DATACK outputs enter a high
impedance state.
124
DATACK_B Digital
Output
Data Output Clock Invert. See DATACK description.
Data Outputs
113-120
D
R_A(7:0)
Digital
Output
Red Port A (V or U/V) Output Data. Converted pixel data is presented at
the data output port synchronous with the DATACK and HSOUT signals.
As the pixel sample phase is adjusted, the HSOUT, DATACK and data
outputs all shift together. In single channel mode, all data is presented at
the A output ports. In dual channel mode, output data is presented at A
and B outputs, either in alternating (interleaved mode) or simultaneous
(parallel mode ) timing. When 4:2:2 pulldown mode is enabled, only the A
ports are used, with U/V data output on Red Port A, and Y data output on
Green Port A. When the chip is in seek mode, or low power mode, all data
outputs are placed in a high impedance state. See the applications section
and configuration registers section for more information.
103-110
D
R_B(7:0)
Digital
Output
Red Port B (V) Output Data. See D
R_A(7:0).
90-97
D
G_A(7:0)
Digital
Output
Green Port A (Y) Output Data. See D
R_A(7:0).
80-87
D
G_B(7:0)
Digital
Output
Green Port B (Y) Output Datasheet. See D
R_A(7:0).
70-77
D
B_A(7:0)
Digital
Output
Blue Port A (U) Output Data. See D
R_A(7:0).
57-64
D
B_B(7:0)
Digital
Output
Blue Port B (U) Output Data. See D
R_A(7:0).
Voltage Reference Bypass
2
REF
BYPASS
Analog
Bypass
Internal Reference Bypass. A 0.1 µF capacitor will be connected from this
pin to ground, to provide a low impedance decoupling for the internal
1.23V bandgap voltage reference.
9R
MIDSCV
(NC)
Analog
Bypass
Red (V) Channel midscale Voltage Bypass. No external bypass is required
for the midscale voltage. Therefore, this pin is not connected to the internal
circuitry. To maintain compatibility with other designs external capacitors
can be connected without affecting operation, performance, or reliability.
24
B
MIDSCV
(NC)
Analog
Bypass
Blue (U) Channel midscale Voltage Bypass. No external bypass is required
for the midscale voltage. Therefore, this pin is not connected to the internal
circuitry. To maintain compatibility with other designs external capacitors
can be connected without affecting operation, performance, or reliability.
PLL Loop Filter
50
FILT
PLL VCO
Bypass
Phase Locked Loop - Voltage Controlled Oscillator filter connection. An
R/C filter circuit is used to maintain the VCO control voltage. This circuit
should be isolated from all other circuitry to minimize clock jitter. The circuit
is connected to the PV
D bus to provide the maximum isolation from noisy
power and ground buses. Refer to the applications section for more
information.
www.national.com
6


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