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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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HCF40105BEY Fiches technique(PDF) 8 Page - STMicroelectronics |
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HCF40105BEY Fiches technique(HTML) 8 Page - STMicroelectronics |
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8 / 12 page  LOADING DATA Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momen- tarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred tothe second location. The flag will remain low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. UNLOADING DATA As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by afalling edge on theSO input. This fall- ing edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are avail- able in the FIFO, the DOR signal will go high again sig- nifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any fur- ther commands will be ignored until a ”1” marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3- state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on)while the SHIFT-OUT is at logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. CASCADING The HCC/HCF40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in par- allel, if expanding is done in both directions. 3-STATE OUTPUTS In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load con- dition of the register can be detected by the state of the DOR output. MASTER RESET A high on the MASTER RESET (MR) sets all the con- trol logic marker bits to ”0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be super- seded when the first word is loaded. APPLICATIONS INFORMATION EXPANSION, 8 BITS–WIDE–BY–16 N–BITS LONG. HCC/HCF40105B 8/12 |
Numéro de pièce similaire - HCF40105BEY |
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Description similaire - HCF40105BEY |
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