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MC100ES6254AC Fiches technique(PDF) 5 Page - Integrated Device Technology

No de pièce MC100ES6254AC
Description  2.5/3.3V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
Download  9 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

MC100ES6254AC Fiches technique(HTML) 5 Page - Integrated Device Technology

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MC100ES6254/D
TIMING SOLUTIONS
5
a.
AC characteristics apply for parallel output termination of 50
Ω to V
TT.
b.
VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
c.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range
and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and
part-to-part skew.
d.
The MC100ES6254 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz.
e.
Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
f.
Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
g.
Propagation delay OE assertion to output enabled (active).
Table 7. AC CHARACTERISTICS (VCC = 3.3 V ± 5% or 2.5 V ± 5%, TJ = 0° to +110°C)
a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VPP
Differential input voltageb (peak-to-peak)
0.3
1.3
V
VCMR
Differential input crosspoint voltagec
1.2
VCC-0.3
V
VO(P-P)
Differential output voltage (peak-to-peak)
fO < 1.1 GHz
fO < 2.5 GHz
fO < 3.0 GHz
0.45
0.35
0.20
0.7
0.55
0.35
V
V
V
fCLK
Input Frequency
0
3000d
MHz
tPD
Propagation delay CLK, 1 to QA[] or QB[]
360
485
610
ps
Differential
tsk(O)
Output-to-output skew
50
ps
Differential
tsk(PP)
Output-to-output skew(part-to-part)
250
ps
Differential
tSK(P)
DCO
Output pulse skewe
Output duty cycle
tREF < 100 MHz
tREF < 800 MHz
49.4
45.2
60
50.6
54.8
ps
%
%
DCfref = 50%
DCfref = 50%
tJIT(CC)
Output cycle-to-cycle jitter
RMS (1
σ)
1
ps
SEL0
≠ SEL1
tr, tf
Output Rise/Fall Time
0.05
300
ps
20% to 80%
tPDLf
Output disable time
2.5
⋅T + t
PD
3.5
⋅T + t
PD
ns
T = CLK period
tPLDg
Output enable time
3
⋅T + t
PD
4
⋅T + t
PD
ns
T = CLK period
tPDL (OEX to Qx[])
50%
tPLD (OEX to Qx[])
Outputs disabled
CLKX
CLKX
OEX
Qx[]
Qx[]
Figure 3. MC100ES6254 output disable/enable timing
Figure 4. MC100ES6254 AC test reference
Differential
Pulse Generator
Z = 50
RT = 50 Ω
ZO = 50 Ω
DUT
MC100ES62
VTT
RT = 50 Ω
ZO = 50 Ω
VTT
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC100ES6254
2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
NETCOM
IDT™ 2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6254
5


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