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CD74HCT75EE4 Fiches technique(PDF) 1 Page - Texas Instruments |
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CD74HCT75EE4 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 17 page 1 Data sheet acquired from Harris Semiconductor SCHS135F Features • True and Complementary Outputs • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected. Pinout CD54HC75, CD54HCT75 (CERDIP) CD74HC75 (PDIP, SOIC, SOP, TSSOP) CD74HCT75 (PDIP, SOIC, TSSOP) TOP VIEW Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC75F3A -55 to 125 16 Ld CERDIP CD54HCT75F3A -55 to 125 16 Ld CERDIP CD74HC75E -55 to 125 16 Ld PDIP CD74HC75M -55 to 125 16 Ld SOIC CD74HC75MT -55 to 125 16 Ld SOIC CD74HC75M96 -55 to 125 16 Ld SOIC CD74HC75NSR -55 to 125 16 Ld SOP CD74HC75PW -55 to 125 16 Ld TSSOP CD74HC75PWR -55 to 125 16 Ld TSSOP CD74HCT75E -55 to 125 16 Ld PDIP CD74HCT75M -55 to 125 16 Ld SOIC CD74HCT75PWT -55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 1Q0 1D0 1D1 2E VCC 2D0 2Q1 2D1 1Q0 1Q1 1E GND 2Q0 2Q0 2Q1 1Q1 March 1998 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Dual 2-Bit Bistable Transparent Latch [ /Title (CD74 HC75, CD74 HCT75 ) /Sub- ject (Dual 2-Bit Bistabl e |
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