74VHC125T datasheet(1/8 Pages) STMICROELECTRONICS

No de pièce	74VHC125T

Description	QUAD BUS BUFFERS 3-STATE

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74VHC125

QUAD BUS BUFFERS (3-STATE)

PRELIMINARY DATA

June 1999

PIN CONNECTION AND IEC LOGIC SYMBOLS

s

HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC =5V

s

LOW POWER DISSIPATION:

ICC =4

µA (MAX.) at TA =25 oC

s

HIGH NOISE IMMUNITY:

VNIH =VNIL =28% VCC (MIN.)

s

POWER DOWN PROTECTION ON INPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|=IOL = 8 mA (MIN)

s

BALANCED PROPAGATION DELAYS:

tPLH

≅ tPHL

s

OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 5.5V

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 125

s

IMPROVED LATCH-UP IMMUNITY

s

LOW NOISE: VOLP = 0.8V (Max.)

DESCRIPTION

The 74VHC125 is an advanced high-speed

CMOS QUAD BUS BUFFERS fabricated with

sub-micron silicon gate and double-layer metal

wiring C

2MOS technology.

This device requires the 3-STATE control input G

to be set high to place the output into the high

impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2kV ESD immunity and transient excess

voltage.

ORDER CODES :

74VHC125M

74VHC125T

M

(Micro Package)

T

(TSSOP Package)

®

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