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SN74ACT2228DWR Fiches technique(PDF) 9 Page - Texas Instruments |
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SN74ACT2228DWR Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 15 page SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 through 3) MIN MAX UNIT fclock Clock frequency 22 MHz t Pulse duration 1WRTCLK, 2WRTCLK high or low 15 ns tw Pulse duration 1RDCLK, 2RDCLK high or low 15 ns 1D before 1WRTCLK ↑ and 2D before 2WRTCLK↑ 6 1WRTEN before 1WRTCLK ↑ and 2WRTEN before 2WRTCLK↑ 6 tsu Setup time 1RDEN before 1RDCLK ↑ and 2RDEN before 2RDCLK↑ 6 ns 1RESET low before 1WRTCLK ↑ and 2RESET low before 2WRTCLK↑† 6 1RESET low before 1RDCLK ↑ and 2RESET low before 2RDCLK↑† 6 1D after 1WRTCLK ↑ and 2D after 2WRTCLK↑ 0 1WRTEN after 1WRTCLK ↑ and 2WRTEN after 2WRTCLK↑ 0 th Hold time 1RDEN after 1RDCLK ↑ and 2RDEN after 2RDCLK↑ 0 ns 1RESET low after 1WRTCLK ↑ and 2RESET low after 2WRTCLK↑† 6 1RESET low after 1RDCLK ↑ and 2RESET low after 2RDCLK↑† 6 † Requirement to count the clock edge as one of at least four needed to reset a FIFO switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT fmax 1WRTCLK, 2WRTCLK, or 1RDCLK, 2RDCLK 22 MHz 1RDCLK ↑, 2RDCLK↑ 1Q, 2Q 2 20 1WRTCLK ↑, 2WRTCLK↑ 1IR, 2IR 1 20 tpd 1RDCLK ↑, 2RDCLK↑ 1OR, 2OR 1 20 ns 1WRTCLK ↑, 2WRTCLK↑ 1AF/AE 2AF/AE 3 20 1RDCLK ↑, 2RDCLK↑ 1AF/AE, 2AF/AE 3 20 tPLH 1WRTCLK ↑, 2WRTCLK↑ 1HF 2HF 2 20 ns tPHL 1RDCLK ↑, 2RDCLK↑ 1HF, 2HF 3 20 ns tPLH 1RESET 2RESET low 1AF/AE, 2AF/AE 1 20 ns tPHL 1RESET, 2RESET low 1HF, 2HF 1 20 ns |
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