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74AC74 Fiches technique(PDF) 1 Page - STMicroelectronics |
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74AC74 Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 11 page 74AC74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR April 1997 s HIGH SPEED: fMAX = 300 MHz (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA =25 oC s HIGH NOISE IMMUNITY: VNIH =VNIL = 28% VCC (MIN.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =24 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The AC74 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES : 74AC74B 74AC74M M (Micro Package) B (Plastic Package) 1/11 |
Numéro de pièce similaire - 74AC74 |
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Description similaire - 74AC74 |
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