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TS61C20CXRF Fiches technique(PDF) 5 Page - Taiwan Semiconductor Company, Ltd |
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TS61C20CXRF Fiches technique(HTML) 5 Page - Taiwan Semiconductor Company, Ltd |
5 / 7 page TS61 Series Voltage Detector 5/7 Version: A07 Oscillation Description (Continue) OUTPUT CURRENT OSCILLATION WITH THE CMOS OUTPUT CONFIGURATION Since the TS61 series are CMOS ICs, through current will flow when the IC’s internal circuit switching operates (during release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through current’s resistor (RIN) during release voltage operations (refer to diagram 2). Since hysteresis exists during detect operation, oscillation is unlikely to occur. Diagram 2: Oscillation in relation to through current Function Description 1. When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN. (A condition of high impedance exists with N-ch open drain output configurations). 2. When input voltage (VIN) falls below detect voltage (VDF), output voltage will be equal to the ground voltage (VSS). 3. When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become unstable. In this condition, VIN will equal the pulled-up output (should output be pull-up). 4. When input voltage (VIN) rises above the ground voltage (VSS) level, output will be unstable at levels below the minimum operating voltage (VMIN). Between the VMIN and detect release voltage VDR level, the ground voltage (VSS) level will be maintained. 5. When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN. (A condition of high impedance exists with N-ch open drain output configurations.) 6. The difference between VDR and VDF represents the hysteresis range. Timing Chart |
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Description similaire - TS61C20CXRF |
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